PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual 2.3.3. Exclusive cache configuration

2.3.3. Exclusive cache configuration

Setting the exclusive cache configuration bit in the Auxiliary Control Register to 1 configures the L2 cache to behave as an exclusive cache relative to the L1 cache. The exclusive cache mechanism only applies to the outer write-back inner write-back data transactions received by the cache controller slave ports, that is, ARCACHESx/AWCACHESx = ARUSER[4:1]/AWUSER[4:1] = 1011 or 0111 or 1111.

Reads

For reads, the behavior is as follows:

In case of a hit, the line is marked as non-valid, that is, the Tag RAM valid bit is reset, and the dirty bit is unchanged. Future accesses can still hit in this cache line but the line is part of the preferred choice for future evictions.
In case of a miss, the line is not allocated into the L2 cache.

Writes

For writes, the behavior depends on the value of AWUSERSx[9:8]. AWUSERSx[8] indicates that the write transaction is an eviction from the L1 memory system. AWUSERSx[9] indicates if this eviction is clean.

In case of a hit, the line is marked dirty unless AWUSERSx[9:8] = 11. In this case, the dirty bit is unchanged.
In case of a miss, if AWUSERSx[8] is HIGH, the cache line is allocated and its dirty status depends on the value of AWUSERSx[9]. If AWUSERSx[8] is LOW, the cache line is allocated only if it is write allocate.

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