PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual A.1. Clock and reset

PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual

Revision: r1p0

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A.1. Clock and reset

Table A.1 shows the clock and reset signals.

Table A.1. Clock and reset signals

Signal	Type	Description
CLK	Input	Main clock
CLKOUT	Output	Global clock signal for RAMs
DATACLKEN	Input	Clock enable for Data RAM interface
DATACLKOUT	Output	Clock for Data RAM
DATACLKOUTEN	Output	Clock enable for Data RAM clock
IDLE	Output	Indicates cache controller is idle
INCLKENM0	Input	Clock enable for M0 AXI inputs
INCLKENM1	Input	Clock enable for M1 AXI inputs
INCLKENS0	Input	Clock enable for S0 AXI inputs
INCLKENS1	Input	Clock enable for S1 AXI inputs
nRESET	Input	Global reset, active LOW
OUTCLKENM0	Input	Clock enable for M0 AXI outputs
OUTCLKENM1	Input	Clock enable for M1 AXI outputs
OUTCLKENS0	Input	Clock enable for S0 AXI outputs
OUTCLKENS1	Input	Clock enable for S1 AXI outputs
TAGCLKEN	Input	Clock enable for Tag RAM interface
TAGCLKOUT	Output	Clock for Tag RAM
TAGCLKOUTEN	Output	Clock enable for Tag RAM clock

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