Master port 1 is only implemented in a two-master configuration. Table A.6 shows the master
port 1 signals.
Table A.6. Master port 1 signals
| Signal | Type | Description |
|---|
| ARADDRM1[31:0] | Output | Address bus |
| ARBURSTM1[1:0] | Output | Burst type |
| ARCACHEM1[3:0] | Output | Cache information |
| ARIDM1[`pl310_AXI_ID_MAX+2:0] | Output | Address ID |
| ARLENM1[3:0] | Output | Burst length |
| ARLOCKM1[1:0] | Output | Lock type |
| ARPROTM1[2:0] | Output | Protection information |
| ARREADYM1 | Input | Address accepted |
| ARSIZEM1[2:0] | Output | Burst size |
| ARVALIDM1 | Output | Address valid |
| AWADDRM1[31:0] | Output | Address bus |
| AWBURSTM1[1:0] | Output | Burst type |
| AWCACHEM1[3:0] | Output | Cache information |
| AWIDM1[`pl310_AXI_ID_MAX+2:0] | Output | Address ID |
| AWLENM1[3:0] | Output | Burst length |
| AWLOCKM1[1:0] | Output | Lock type |
| AWPROTM1[2:0] | Output | Protection information |
| AWREADYM1 | Input | Address accepted |
| AWSIZEM1[2:0] | Output | Burst size |
| AWVALIDM1 | Output | Address valid |
| BIDM1[`pl310_AXI_ID_MAX+2:0] | Input | Write ID |
| BREADYM1 | Output | Write response accepted |
| BRESPM1[1:0] | Input | Write response |
| BVALIDM1 | Input | Write response valid |
| RDATAM1[63:0] | Input | Read data bus |
| RIDM1[`pl310_AXI_ID_MAX+2:0] | Input | Read ID |
| RLASTM1 | Input | Read last transfer |
| RREADYM1 | Output | Read accepted |
| RRESPM1[1:0] | Input | Read response |
| RVALIDM1 | Input | Read data valid |
| WDATAM1[63:0] | Output | Write data bus |
| WIDM1[`pl310_AXI_ID_MAX+2:0] | Output | Write ID |
| WLASTM1 | Output | Write last transfer |
| WREADYM1 | Input | Write data accepted |
| WSTRBM1[7:0] | Output | Write strobes |
| WVALIDM1 | Output | Write data valid |
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