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Table 2.4 shows the general behavior of the cache controller depending on ARMv6 and ARMv7 transactions.
Table 2.4. Cache operation descriptions
| AXI transaction | ARMv6 and ARMv7 memory type attribute | Cache controller behavior |
|---|---|---|
| Noncacheable, nonbufferable | Strongly ordered | Read: Not cached in L2, results in L3 access. Write: Not buffered, results in L3 access. |
| Bufferable only | Device | Read: Not cached in L2, results in L3 access. Write: Put in store buffer, not merged, immediately drained to L3. |
| Cacheable but do not allocate | Outer non cacheable | Read: Not cached in L2, results in L3 access. Write: Put in store buffer, write to L3 when store buffer is drained. |
| Cacheable and bufferable but do not allocate | ||
| Cacheable write-through, allocate on read | Outer write-through, no write allocate | Read hit: Read from L2. Read miss: Linefill to L2. Write hit: Put in store buffer, write to L2 and L3 when store buffer is drained. Write miss: Put in store buffer, write to L3 when store buffer is drained. |
| Cacheable write-back, allocate on read | Outer write-back, no write allocate | Read hit: Read from L2. Read miss: Linefill to L2. Write hit: Put in store buffer, write to the L2 when store buffer is drained, mark line as dirty. Write miss: Put in store buffer, write to L3 when store buffer is drained. |
| Cacheable write-through, allocate on write | Read hit: Read from L2. Read miss: Not cached in L2, causes L3 access. Write hit: Put in store buffer, write to L2 and L3 when store buffer is drained. Write miss: Put in store buffer, data request for word/line to L3 if not full when store buffer is drained, allocation to L2, write to L3. | |
| Cacheable write-back, allocate on write | Read hit: Read from L2. Read miss: Not cached in L2, causes L3 access. Write hit: Put in store buffer, write to the L2 when store buffer is drained, mark line as dirty. Write miss: Put in store buffer, data request for word/line to L3 if line not full, allocation to L2 when store buffer is drained. | |
| Cacheable write-through, allocate on read and write | Outer write-through, allocate on both reads and writes | Read hit: Read from L2. Read miss: Linefill to L2. Write hit: Put in store buffer, write to L2 and L3 when store buffer is drained. Write miss: Put in store buffer, data request for word/line to L3 if line not full, allocation to L2 when store buffer is drained, write to L3. |
| Cacheable write-back, allocate on read and write | Outer write-back, write allocate | Read hit: Read from L2. Read miss: Linefill to L2. Write hit: Put in store buffer, write to L2 when store buffer is drained, mark line as dirty. Write miss: Put in store buffer, data request for word/line to L3 if line not full, allocation to L2 when store buffer is drained. |
You can modify the default behavior described in Table 2.4 using various parameters, such as shared attribute, force write allocate, and exclusive cache configuration.
Other behaviors are described in:
| Copyright © 2007, 2008 ARM Limited. All rights reserved. | ARM DDI 0246B |
| Non-Confidential | |
| PDF version | |
| Home > Functional Overview > Cache operation |