Figure 2.3 shows cache controller parity and RAM error support. The cache controller generates the parity write data for the data and tag RAMs. For:

Because only one tag RAM is written at any one time, only one bit is required.

In addition to parity error detection, there are error inputs on the RAM interface, one from Data, DATAERR and eight from tag RAM, TAGERR. You can use them to identify read and write errors from the RAMs. Those errors are treated in the same way as parity errors.

If a parity error occurs on tag or data RAM during AXI read transactions, a SLVERR response is reported back to RRESPSx through the event bus.

If a parity error occurs on tag or data RAM during AXI write transactions, a SLVERR response is reported back to the L1 through an interrupt on the SLVERRINTR line.

For cache maintenance operations, if a parity error occurs on tag or data RAM, the error is reported back through the interrupt lines only.

Figure 2.3 shows the cache controller parity and RAM error support.