PrimeCell Level 2 Cache Controller (PL310) Technical ReferenceManual

Revision: r1p0


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the cache controller
1.1.1. Features
1.2. Typical system configuration
1.3. Product revisions
2. Functional Overview
2.1. AXI master and slave interfaces
2.1.1. Clock enable usage model in the cache controller AXIinterfaces
2.2. Cache attributes
2.3. Cache operation
2.3.1. Shared attribute
2.3.2. Force write allocate
2.3.3. Exclusive cache configuration
2.4. AXI locked and exclusive accesses
2.4.1. AXI locked transfers
2.4.2. AXI exclusive accesses
2.5. Master and slave port IDs
2.6. Exported AXI control
2.7. TrustZone support in the cache controller
2.8. Power modes
2.8.1. Run mode
2.8.2. Standby mode
2.8.3. Dormant mode
2.8.4. Shutdown mode
2.9. Implementation details
2.9.1. Disabled operation
2.9.2. Store buffer operation
2.9.3. Cache configurability
2.9.4. Hazards
2.9.5. External error support for L3 memory
2.9.6. Cache event monitoring
2.9.7. Cache interrupts outputs
2.9.8. Parity and RAM error support
2.9.9. Error signalling and handling
2.9.10. Cacheable read requests on AXI slaveports
2.9.11. Write access from the store buffer
2.9.12. AXI master or store buffer allocationrequests
2.9.13. Clean maintenance
2.9.14. Invalidate maintenance operation
2.9.15. Clean and Invalidate maintenance operation
2.10. MBIST support
2.11. RAM organization
2.11.1. Data RAM
2.11.2. Tag RAM
2.11.3. Parity RAM
2.11.4. RAM bus usage versus cache associativityand way size
2.12. RAM clocking and latencies
2.12.1. RAM clocking
2.12.2. RAM latencies
3. Programmer’s Model
3.1. About the programmer’s model
3.1.1. Initialization sequence
3.2. Summary of registers
3.3. Register descriptions
3.3.1. Register 0, Cache ID Register
3.3.2. Register 0, Cache Type Register
3.3.3. Register 1, Control Register
3.3.4. Register 1, AuxiliaryControl Register
3.3.5. Register 1, Tag and Data RAM LatencyControl Registers
3.3.6. Register 2, Event Counter ControlRegister
3.3.7. Register 2, Event Counter ConfigurationRegisters
3.3.8. Register 2, Event Counter Value Registers
3.3.9. Register 2, Interrupt Registers
3.3.10. Register 7, Cache Maintenance Operations
3.3.11. Register 9, Cache Lockdown
3.3.12. Register 12, Address Filtering
3.3.13. Register 15, Debug Register
A. Signal Descriptions
A.1. Clock and reset
A.2. Configuration
A.3. Slave and master ports
A.3.1. Slave port 0
A.3.2. Slave port 1
A.3.3. Master port 0
A.3.4. Master port 1
A.4. RAM interface
A.4.1. Data RAM interface
A.4.2. Tag RAM interface
A.5. Cache event monitoring
A.6. Cache interrupt
A.7. MBIST interface
B. AC Parameters
B.1. Reset and configuration signal timingparameters
B.2. Slave port 0 I/O signal timing parameters
B.3. Slave port 1 I/O signal timing parameters
B.4. Master port 0 I/O signal timing parameters
B.5. Master port 1 I/O signal timing parameters
B.6. RAMs signal timing parameters
B.6.1. Data RAM
B.6.2. Tag RAM
B.7. Event monitor signal timing parameters
B.8. Cache interrupt ports signal timing parameters
B.9. MBIST interface signal timing parameters
C. Timing Diagrams
C.1. Single read hit transaction
C.2. Single read miss transaction
C.3. Single noncacheable read transaction
C.4. Outstanding read hit transaction
C.5. Hit under miss read transactions
C.6. Single bufferable write transaction
C.7. Single nonbufferable write transaction
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Top level diagram
1.2. Example cache controller interfacedto an ARM processor
2.1. CLKEN used to drive cache controllerinputs in case of integer clock ratio
2.2. Clock enable usage model for 1.5:1clock ratio in master port
2.3. Parity and RAM error support fora 16-way implementation
2.4. MBIST interface for 16-way implementation,with parity, without lockdown by line
2.5. Data RAM organization for 16 ways
2.6. Tag RAM organization for 16 ways,with parity, without lockdown by line
2.7. Data parity RAM organization
2.8. Data RAM address bus format for 16ways
2.9. Tag RAM running at slower frequency
2.10. Tag RAM clock gating
2.11. Tag RAM setup latency
2.12. Tag RAM read access latency
2.13. Tag RAM write access latency
3.1. Cache ID Register bit assignments
3.2. Cache Type Register bit assignments
3.3. Control Register bit assignments
3.4. Auxiliary Control Register bit assignments
3.5. Tag and Data RAM Latency ControlRegister bit assignments
3.6. Event Counter Control Register bitassignments
3.7. Event Counter Configuration Registerbit assignments
3.8. Interrupt Register bit assignments
3.9. Physical address format
3.10. Index/way format
3.11. Format C lockdown
3.12. Address Filtering Start Registerbit assignments
3.13. Address Filtering End Register bitassignments
3.14. Debug Control Register bit assignments
C.1. Single read hit transaction
C.2. Single read miss transaction
C.3. Single noncacheable read transaction
C.4. Outstanding read hit transaction
C.5. Hit under miss read transaction
C.6. Single bufferable write transaction
C.7. Single nonbufferable write transaction

List of Tables

1.1. Typical memory sizes and access times
1.2. RTL options
1.3. Master port transactions for a two master port system
2.1. AXI master interface attributes
2.2. AXI slave interface attributes
2.3. AWCACHE and ARCACHE definitions
2.4. Cache operation descriptions
2.5. Master port ID values for writes
2.6. Master port ID values for reads
2.7. Exported master ports AXI control signals
2.8. Cache controller cache configurability
2.9. Error responses for all combinations of L3 access
2.10. Event pins
2.11. Interrupts
2.12. Cacheable read requests on AXI slave ports
2.13. Write-through/write-back write access from store buffer
2.14. AXI M0 and AXI M1 masters or store buffer allocation requests
2.15. Clean maintenance operation cases
2.16. Invalidate maintenance operation cases
2.17. Clean and Invalidate maintenance operation cases
2.18. RAM clock enables
3.1. Cache controller register map
3.2. Summary of cache controller registers
3.3. Cache ID Register bit assignments
3.4. Cache Type Register bit assignments
3.5. Control Register bit assignments
3.6. Auxiliary Control Register bit assignments
3.7. Tag and Data RAM Latency Control Register bit assignments
3.8. Event Counter Control Register bit assignments
3.9. Event Counter Configuration Register bit assignments
3.10. Event Counter 1 Value Register bit assignments
3.11. Interrupt Mask Register bit assignments
3.12. Masked Interrupt Status Register bit assignments
3.13. Raw Interrupt Status Register bit assignments
3.14. Interrupt Clear Register bit assignments
3.15. Maintenance operations
3.16. Cache maintenance operations
3.17. Cache lockdown
3.18. Lockdown by Line Enable Register bit assignments
3.19. Unlock All Lines Register bit assignments
3.20. Data Lockdown 0 Register, offset 0x900
3.21. Instruction Lockdown 0 Register, offset 0x904
3.22. Data Lockdown 1 Register, offset 0x908
3.23. Instruction Lockdown 1 Register, offset 0x90C
3.24. Data Lockdown 2 Register, offset 0x910
3.25. Instruction Lockdown 2 Register, offset 0x914
3.26. Data Lockdown 3 Register, offset 0x918
3.27. Instruction Lockdown 3 Register, offset 0x91C
3.28. Data Lockdown 4 Register, offset 0x920
3.29. Instruction Lockdown 4 Register, offset 0x924
3.30. Data Lockdown 5 Register, offset 0x928
3.31. Instruction Lockdown 5 Register, offset 0x92C
3.32. Data Lockdown 6 Register, offset 0x930
3.33. Instruction Lockdown 6 Register, offset 0x934
3.34. Data Lockdown 7 Register, offset 0x938
3.35. Instruction Lockdown 7 Register, offset 0x93C
3.36. Address Filtering Start Register bit assignments
3.37. Address Filtering End Register bit assignments
3.38. Debug Control Register bit assignments
A.1. Clock and reset signals
A.2. Configuration signals
A.3. Slave port 0 signals
A.4. Slave port 1 signals
A.5. Master port 0 signals
A.6. Master port 1 signals
A.7. Data RAM interface signals
A.8. Tag RAM interface
A.9. Cache event monitoring signals
A.10. Cache Interrupt signals
A.11. MBIST interface signals
B.1. Reset and configuration
B.2. Slave port 0 I/O
B.3. Slave port 1 I/O
B.4. Master port 0 I/O
B.5. Master port 1 I/O
B.6. Data RAM
B.7. Tag RAM
B.8. Event monitor
B.9. Cache interrupt ports
B.10. MBIST interface signal

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This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

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ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A 30November 2007 First release for r0p0
Revision B 04April 2008 First release for r1p0
Copyright © 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0246B
Non-Confidential