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These registers can prevent new addresses from being allocated and can also prevent data from being evicted out of the L2 cache. Such behavior can distinguish instructions from data transactions.
Cache maintenance operations that invalidate, clean, or clean and invalidate cache contents affect locked-down cache lines as normal.
This register has read-only or read and write permission, depending on the security state you have selected for the register access and on the Non-Secure Lockdown Enable bit in the Auxiliary Control Register. Table 3.17 shows the different settings of the Cache Lockdown Register.
Table 3.17. Cache lockdown
| Security of register access | Non-Secure Lockdown Enable bit | Permission |
|---|---|---|
| Secure | 0, this is the default value 1 | Read and write Read and write |
| Non-Secure | 0, this is the default value 1 | Read only Read and write |
On reset the Non-Secure Lockdown Enable bit is set to 0 and Lockdown Registers are not permitted to be modified by non-secure accesses. In that configuration, if a non-secure access tries to write to those registers, the write response returns a DECERR response. This decode error results in the registers not being updated.
When permitted, the non-secure lockdown functionality can be identical to the secure one.
There are two lockdown schemes, line-based and way-based.
The following two registers enable the use of this optional lockdown by line feature:
Lockdown by Line Enable Register. See Table 3.18.
Unlock All Lines Register. See Table 3.19.
If you try to launch a background cache maintenance operation when the cache controller is performing an unlock all lines operation the controller returns SLVERR.
Table 3.18. Lockdown by Line Enable Register bit assignments
| Bits | Field | Description |
|---|---|---|
| [31:1] | Reserved | SBZ/RAZ |
| [0] | lockdown_by_line_enable | 0 = Lockdown by line disabled. This is the default. 1 = Lockdown by line disabled. |
Table 3.19. Unlock All Lines Register bit assignments
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | SBZ/RAZ |
| [15:0] | unlock_all_lines_by_way_operation | For all bits: 0 = Unlock all lines disabled. This is the default. 1 = Unlock all lines operation in progress for the corresponding way. |
To control the cache lockdown by way and the cache lockdown by master mechanisms see the tables from Table 3.20 to Table 3.35. See also Lockdown by way.
Table 3.20. Data Lockdown 0 Register, offset 0x900
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | DATALOCK000 | Use when AR/WUSERSx[7:5] = 000 |
Table 3.21. Instruction Lockdown 0 Register, offset 0x904
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | INSTRLOCK000 | Use when AR/WUSERSx[7:5] = 000 |
Table 3.22. Data Lockdown 1 Register, offset 0x908
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | DATALOCK001 | Use when AR/WUSERSx[7:5] = 001 |
Table 3.23. Instruction Lockdown 1 Register, offset 0x90C
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | INSTRLOCK001 | Use when AR/WUSERSx[7:5] = 001 |
Table 3.24. Data Lockdown 2 Register, offset 0x910
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | DATALOCK010 | Use when AR/WUSERSx[7:5] = 010 |
Table 3.25. Instruction Lockdown 2 Register, offset 0x914
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | INSTRLOCK010 | Use when AR/WUSERSx[7:5] = 010 |
Table 3.26. Data Lockdown 3 Register, offset 0x918
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | DATALOCK011 | Use when AR/WUSERSx[7:5] = 011 |
Table 3.27. Instruction Lockdown 3 Register, offset 0x91C
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | INSTRLOCK011 | Use when AR/WUSERSx[7:5] = 011 |
Table 3.28. Data Lockdown 4 Register, offset 0x920
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | DATALOCK100 | Use when AR/WUSERSx[7:5] = 100 |
Table 3.29. Instruction Lockdown 4 Register, offset 0x924
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | INSTRLOCK100 | Use when AR/WUSERSx[7:5] =100 |
Table 3.30. Data Lockdown 5 Register, offset 0x928
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | DATALOCK101 | Use when AR/WUSERSx[7:5] = 101 |
Table 3.31. Instruction Lockdown 5 Register, offset 0x92C
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | INSTRLOCK101 | Use when AR/WUSERSx[7:5] = 101 |
Table 3.32. Data Lockdown 6 Register, offset 0x930
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | DATALOCK110 | Use when AR/WUSERSx[7:5] = 110 |
Table 3.33. Instruction Lockdown 6 Register, offset 0x934
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | INSTRLOCK110 | Use when AR/WUSERSx[7:5] = 110 |
Table 3.34. Data Lockdown 7 Register, offset 0x938
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | DATALOCK111 | Use when AR/WUSERSx[7:5] = 111 |
Table 3.35. Instruction Lockdown 7 Register, offset 0x93C
| Bits | Field | Description |
|---|---|---|
| [31:16] | Reserved | RAZ |
| [15:0] | INSTRLOCK111 | Use when AR/WUSERSx[7:5] = 111 |
If the pl310_16_WAYS option
is not implemented, bits [15:8] are reserved in all the Data and
Instruction Lockdown registers.
The Data and Instruction Lockdown 1-7 registers
are not used if the option pl310_LOCKDOWN_BY_MASTER is
not enabled. This corresponds to the simple Lockdown by Way, see Lockdown by way.
The cache controller uses a pseudo-random replacement strategy. A deterministic replacement strategy can be achieved when you use the lockdown registers. The pseudo-random replacement strategy fills invalid and unlocked ways first. For each line, when ways are either valid or locked, the victim is chosen as the next unlocked way.
If you require a deterministic replacement strategy, the lockdown registers are used to prevent ways from being allocated. For example, if the L2 size is 256KB, and each way is 32KB, and a piece of code is required to reside in two ways of 64KB, with a deterministic replacement strategy, then ways 1-7 must be locked before the code is filled into the L2 cache. If the first 32KB of code is allocated into way 0 only, then way 0 must be locked and way 1 unlocked so that the second half of the code can be allocated in way 1.
There are two lockdown registers, one for data and one for instructions. If required, you can separate data and instructions into separate ways of the L2 cache.
If pl310_LOCKDOWN_BY_MASTER is implemented,
there are 16 lockdown registers.
| Copyright © 2007, 2008 ARM Limited. All rights reserved. | ARM DDI 0246C |
| Non-Confidential | |
| PDF version | |
| Home > Programmers Model > Register descriptions > Cache Lockdown |