PrimeCell Level 2 Cache Controller (PL310) Technical Reference ManualRevision: r2p0
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3.3.1. Cache ID Register

The reg0_cache_id Register characteristics are:

Purpose

Returns the 32-bit device ID code it reads off the CACHEID input bus. The value is specified by the system integrator.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.2.

Figure 3.1 shows the reg0_cache_id Register bit assignments.

Figure 3.1. reg0_cache_id Register bit assignments


Table 3.3 shows the reg0_cache_id register bit assignments.

Table 3.3. reg0_cache_id Register bit assignments

BitsFieldDescription
[31:24]Implementer0x41 (ARM)
[23:16]ReservedSBZ
[15:10]CACHE ID-
[9:6]Part number
0x3
[5:0]RTL release0x4

Note

  • Part number 0x3 denotes PrimeCell Level 2 Cache Controller (PL310)

  • RTL release 0x4 denotes r2p0 code of the cache controller. See the Release Note for the value of these bits for other releases.

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