PrimeCell Level 2 Cache Controller (PL310) Technical Reference ManualRevision: r2p0
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3.3.7. Event Counter Configuration Registers

The reg2_ev_counter0_cfg and reg2_ev_counter1_cfg Register characteristics are:

Purpose

Enables event counter 1 and 0 to be driven by a specific event. Counter 1 or counter 0 increments when the event occurs. Cache event monitoring describes the counter event source signals.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.2.

Figure 3.7 shows the reg2_ev_counter0_cfg and reg2_ev_counter1_cfg Register bit assignments.

Figure 3.7. reg2_ev_counter0_cfg and reg2_ev_counter1_cfg Register bit assignments


Table 3.9 shows the reg2_ev_counter0_cfg and reg2_ev_counter1_cfg Register bit assignments.

Table 3.9. reg2_ev_counter0_cfg and reg2_ev_counter1_cfg Register bit assignments

BitsFieldDescription
[31:6]ReservedSBZ/RAZ
[5:2]Counter event sourceEventEncoding
Counter Disabled0000
CO0001
DRHIT0010
DRREQ0011
DWHIT0100
DWREQ0101
DWTREQ0110
IRHIT0111
IRREQ1000
WA1001
PF1010
Counter Disabled1011-1111
[1:0]Event counter interrupt generation

00 = Disabled. This is the default.

01 = Enabled: Increment condition.

10 = Enabled: Overflow condition.

11 = Interrupt generation is disabled.


Note

When the SPNIDEN input pin is LOW the event counters only increment on non-secure events, secure events are not counted unless the SPNIDEN pin signal is configured HIGH.

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