PrimeCell Level 2 Cache Controller (PL310) Technical Reference ManualRevision: r2p0
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2.3. Cache operation

Table 2.7 to Table 2.15 show the general behavior of the cache controller depending on ARMv6 and ARMv7 transactions.

Table 2.7 shows the general behavior of the cache controller for Noncacheable and nonbufferable AXI transactions.

Table 2.7. Noncacheable and nonbufferable AXI transactions

ARMv6 and ARMv7 memory type attributeCache controller behavior
Strongly ordered

Read: Not cached in L2, results in L3 access.

Write: Not buffered, results in L3 access.


Table 2.8 shows the general behavior of the cache controller for Bufferable only AXI transactions.

Table 2.8. Bufferable only AXI transactions

ARMv6 and ARMv7 memory type attributeCache controller behavior
Device

Read: Not cached in L2, results in L3 access.

Write: Put in store buffer, not merged, immediately drained to L3.[1]

[1] Not all types of Device writes go to the store buffer. For example, the L2CC (PL310) treats a Device write that crosses a cache line boundary as a Strongly Ordered access.


Table 2.9 shows the general behavior of the cache controller for Chacheable but do not allocate AXI transactions, and Cacheable and bufferable but do not allocate AXI transactions.

Table 2.9. Cacheable but do not allocate AXI transactions

ARMv6 and ARMv7 memory type attributeCache controller behavior
Outer non cacheable

Read: Not cached in L2, results in L3 access.

Write: Put in store buffer, write to L3 when store buffer is drained.


Table 2.10 shows the general behavior of the cache controller for Cacheable write-through, allocate on read AXI transactions.

Table 2.10. Cacheable write-through, allocate on read AXI transactions

ARMv6 and ARMv7 memory type attributeCache controller behavior
Outer write-through, no write allocate

Read hit: Read from L2.

Read miss: Linefill to L2.

Write hit: Put in store buffer, write to L2 and L3 when store buffer is drained.

Write miss: Put in store buffer, write to L3 when store buffer is drained.


Table 2.11 shows the general behavior of the cache controller for Cacheable write-back, allocate on read AXI transactions.

Table 2.11. Cacheable write-back, allocate on read AXI transactions

ARMv6 and ARMv7 memory type attributeCache controller behavior
Outer write-back, no write allocate

Read hit: Read from L2.

Read miss: Linefill to L2.

Write hit: Put in store buffer, write to the L2 when store buffer is drained, mark line as dirty.

Write miss: Put in store buffer, write to L3 when store buffer is drained.


Table 2.12 shows the general behavior of the cache controller for Cacheable write-through, allocate on write AXI transactions.

Table 2.12. Cacheable write-through, allocate on write AXI transactions

ARMv6 and ARMv7 memory type attributeCache controller behavior
 

Read hit: Read from L2.

Read miss: Not cached in L2, causes L3 access.

Write hit: Put in store buffer, write to L2 and L3 when store buffer is drained.

Write miss:

  • Put in store buffer.

  • When buffer has to be drained, check whether it is full. If it is not full then request word or line to L3 before allocating the buffer to the L2.

  • Allocation to L2.

  • Write to L3.


Table 2.13 shows the general behavior of the cache controller for Cacheable write-back, allocate on write AXI transactions.

Table 2.13. Cacheable write-back, allocate on write AXI transactions

ARMv6 and ARMv7 memory type attributeCache controller behavior
 

Read hit: Read from L2.

Read miss: Not cached in L2, causes L3 access.

Write hit: Put in store buffer, write to the L2 when store buffer is drained, mark line as dirty.

Write miss:

  • Put in store buffer.

  • When buffer has to be drained, check whether it is full. If it is not full then request word or line to L3 before allocating the buffer to the L2.

  • Allocation to L2.


Table 2.14 shows the general behavior of the cache controller for Cacheable write-through, allocate on read and write AXI transactions.

Table 2.14. Cacheable write-through, allocate on read and write AXI transactions

ARMv6 and ARMv7 memory type attributeCache controller behavior
Outer write-through, allocate on both reads and writes

Read hit: Read from L2.

Read miss: Linefill to L2.

Write hit: Put in store buffer, write to L2 and L3 when store buffer is drained.

Write miss:

  • Put in store buffer.

  • When buffer has to be drained, check whether it is full. If it is not full then request word or line to L3 before allocating the buffer to the L2.

  • Allocation to L2.

  • Write to L3.


Table 2.15 shows the general behavior of the cache controller for Cacheable write-back, allocate on read and write AXI transactions.

Table 2.15. Cacheable write-back, allocate on read and write AXI transactions

ARMv6 and ARMv7 memory type attributeCache controller behavior
Outer write-back, write allocate

Read hit: Read from L2.

Read miss: Linefill to L2.

Write hit: Put in store buffer, write to L2 when store buffer is drained, mark line as dirty.

Write miss:

  • Put in store buffer.

  • When buffer has to be drained, check whether it is full. If it is not full then request word or line to L3 before allocating the buffer to the L2.

  • Allocation to L2.


Note

You can modify the default behavior described in Table 2.7 to Table 2.15 using parameters, such as shared attribute, force write allocate, and exclusive cache configuration.

Other behaviors are described in:

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