PrimeCell® Level 2 Cache Controller (PL310) Technical Reference Manual

Revision: r2p0


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the PrimeCell level 2 cache controller (PL310)
1.1.1. Features
1.2. Typical system configuration
1.3. Product revisions
2. Functional Overview
2.1. Cache configurability
2.2. AXI master and slave interfaces
2.2.1. AXI master and slave interface attributes
2.2.2. Clock enable usage model in the cache controller AXI interfaces
2.2.3. Master and slave port IDs
2.2.4. Exported AXI control
2.2.5. AXI locked and exclusive accesses
2.3. Cache operation
2.3.1. Cache attributes
2.3.2. Shared attribute
2.3.3. Force write allocate
2.3.4. Exclusive cache configuration
2.3.5. TrustZone support in the cache controller
2.3.6. Cache Lockdown
2.4. RAM interfaces
2.4.1. RAM organization
2.4.2. RAM clocking and latencies
2.4.3. MBIST support
2.5. Implementation details
2.5.1. Disabled operation
2.5.2. Store buffer operation
2.5.3. Hazards
2.5.4. Cortex-A9 optimizations
2.5.5. External error support for L3 memory
2.5.6. Cache event monitoring
2.5.7. Cache interrupts outputs
2.5.8. Parity and RAM error support
2.6. Power modes
2.6.1. Run mode
2.6.2. Standby mode
2.6.3. Dormant mode
2.6.4. Shutdown mode
3. Programmers Model
3.1. About this programmers model
3.1.1. Initialization sequence
3.2. Register summary
3.3. Register descriptions
3.3.1. Cache ID Register
3.3.2. Cache Type Register
3.3.3. Control Register
3.3.4. Auxiliary Control Register
3.3.5. Tag and Data RAM Latency Control Registers
3.3.6. Event Counter Control Register
3.3.7. Event Counter Configuration Registers
3.3.8. Event Counter Value Registers
3.3.9. Interrupt Registers
3.3.10. Cache Maintenance Operations
3.3.11. Cache Lockdown
3.3.12. Address Filtering
3.3.13. Debug Register
3.3.14. Prefetch Offset Register
A. Signal Descriptions
A.1. Clock and reset
A.2. Configuration
A.3. Slave and master ports
A.3.1. Slave port 0
A.3.2. Slave port 1
A.3.3. Master port 0
A.3.4. Master port 1
A.4. RAM interface
A.4.1. Data RAM interface
A.4.2. Tag RAM interface
A.5. Cache event monitoring
A.6. Cache interrupt
A.7. MBIST interface
B. AC Parameters
B.1. Reset and configuration signal timing parameters
B.2. Slave port 0 I/O signal timing parameters
B.3. Slave port 1 I/O signal timing parameters
B.4. Master port 0 I/O signal timing parameters
B.5. Master port 1 I/O signal timing parameters
B.6. RAMs signal timing parameters
B.6.1. Data RAM
B.6.2. Tag RAM
B.7. Event monitor signal timing parameters
B.8. Cache interrupt ports signal timing parameters
B.9. MBIST interface signal timing parameters
C. Timing Diagrams
C.1. Single read hit transaction
C.2. Single read miss transaction
C.3. Single noncacheable read transaction
C.4. Outstanding read hit transaction
C.5. Hit under miss read transactions
C.6. Single bufferable write transaction
C.7. Single nonbufferable write transaction
D. Revisions
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Top level diagram
1.2. Example cache controller interfaced to an ARM processor
2.1. CLKEN used to drive cache controller inputs in case of integer clock ratio
2.2. Clock enable usage model for 1.5:1 clock ratio in master port
2.3. Driven by cortex a9 cluster with 4 cpus
2.4. Driven by cortex a9 cluster with 1 CPU and ACP
2.5. Data RAM organization for 16 ways
2.6. Tag RAM organization for a 16-way 256KB L2 cache, with parity, with lockdown by line
2.7. Data parity RAM organization
2.8. Data RAM address bus format for 16 ways
2.9. Tag RAM running at slower frequency
2.10. Tag RAM clock gating
2.11. Tag RAM setup latency
2.12. Tag RAM read access latency
2.13. Tag RAM write access latency
2.14. MBIST interface for 16-way implementation, with parity, without lockdown by line
2.15. Parity and RAM error support for a 16-way implementation
3.1. reg0_cache_id Register bit assignments
3.2. reg0_cache_type Register bit assignments
3.3. reg1_control Register bit assignments
3.4. reg1_aux_control Register bit assignments
3.5. reg1_tag_ram_control and reg1_data_ram_control Register bit assignments
3.6. reg2_ev_counter_ctrl Register bit assignments
3.7. reg2_ev_counter0_cfg and reg2_ev_counter1_cfg Register bit assignments
3.8. Interrupt Register bit assignments
3.9. Physical address format
3.10. Index/way format
3.11. Way format
3.12. Address Filtering Start Register bit assignments
3.13. Address Filtering End Register bit assignments
3.14. Debug Control Register bit assignments
3.15. Prefetch Offset Register bit assignments
C.1. Single read hit transaction
C.2. Single read miss transaction
C.3. Single noncacheable read transaction
C.4. Outstanding read hit transaction
C.5. Hit under miss read transaction
C.6. Single bufferable write transaction
C.7. Single nonbufferable write transaction

List of Tables

1.1. Typical memory sizes and access times
1.2. RTL options
1.3. Master port transactions for a two master port system
2.1. Cache controller cache configurability
2.2. AXI master interface attributes
2.3. AXI slave interface attributes
2.4. Master port ID values for writes
2.5. Master port ID values for reads
2.6. Exported master ports AXI control signals
2.7. Noncacheable and nonbufferable AXI transactions
2.8. Bufferable only AXI transactions
2.9. Cacheable but do not allocate AXI transactions
2.10. Cacheable write-through, allocate on read AXI transactions
2.11. Cacheable write-back, allocate on read AXI transactions
2.12. Cacheable write-through, allocate on write AXI transactions
2.13. Cacheable write-back, allocate on write AXI transactions
2.14. Cacheable write-through, allocate on read and write AXI transactions
2.15. Cacheable write-back, allocate on read and write AXI transactions
2.16. AWCACHE and ARCACHE definitions
2.17. MP4 system lockdown register definitions
2.18. MPI plus APC system lockdown register definitions.
2.19. RAM clock enables
2.20. Error responses for all combinations of L3 access
2.21. Event pins
2.22. Interrupts
2.23. Cacheable read requests on AXI slave ports
2.24. Write-through/write-back write access from store buffer
2.25. AXI M0 and AXI M1 masters or store buffer allocation requests
2.26. Clean maintenance operation cases
2.27. Invalidate maintenance operation cases
2.28. Clean and Invalidate maintenance operation cases
3.1. Cache controller register map
3.2. Summary of cache controller registers
3.3. reg0_cache_id Register bit assignments
3.4. reg0_cache_type Register bit assignments
3.5. reg1_control Register bit assignments
3.6. reg1_aux_control Register bit assignments
3.7. reg1_tag_ram_control and reg1_data_ram_control Register bit assignments
3.8. reg2_ev_counter_ctrl Register bit assignments
3.9. reg2_ev_counter0_cfg and reg2_ev_counter1_cfg Register bit assignments
3.10. reg2_ev_counter0 and reg2_ev_counter1 Register bit assignments
3.11. reg2_int_mask Register bit assignments
3.12. Masked Interrupt Status Register bit assignments
3.13. reg2_int_raw_status Register bit assignments
3.14. reg2_int_clear Register bit assignments
3.15. Maintenance operations
3.16. Cache maintenance operations
3.17. Cache lockdown
3.18. Lockdown by Line Enable Register bit assignments
3.19. Unlock All Lines Register bit assignments
3.20. Data Lockdown 0 Register, offset 0x900
3.21. Instruction Lockdown 0 Register, offset 0x904
3.22. Data Lockdown 1 Register, offset 0x908
3.23. Instruction Lockdown 1 Register, offset 0x90C
3.24. Data Lockdown 2 Register, offset 0x910
3.25. Instruction Lockdown 2 Register, offset 0x914
3.26. Data Lockdown 3 Register, offset 0x918
3.27. Instruction Lockdown 3 Register, offset 0x91C
3.28. Data Lockdown 4 Register, offset 0x920
3.29. Instruction Lockdown 4 Register, offset 0x924
3.30. Data Lockdown 5 Register, offset 0x928
3.31. Instruction Lockdown 5 Register, offset 0x92C
3.32. Data Lockdown 6 Register, offset 0x930
3.33. Instruction Lockdown 6 Register, offset 0x934
3.34. Data Lockdown 7 Register, offset 0x938
3.35. Instruction Lockdown 7 Register, offset 0x93C
3.36. Address Filtering Start Register bit assignments
3.37. Address Filtering End Register bit assignments
3.38. Debug Control Register bit assignments
3.39. Prefetch Offset Register bit assignments
A.1. Clock and reset signals
A.2. Configuration signals
A.3. Slave port 0 signals
A.4. Slave port 1 signals
A.5. Master port 0 signals
A.6. Master port 1 signals
A.7. Data RAM interface signals
A.8. Tag RAM interface
A.9. Cache event monitoring signals
A.10. Cache Interrupt signals
A.11. MBIST interface signals
B.1. Reset and configuration
B.2. Slave port 0 I/O
B.3. Slave port 1 I/O
B.4. Master port 0 I/O
B.5. Master port 1 I/O
B.6. Data RAM
B.7. Tag RAM
B.8. Event monitor
B.9. Cache interrupt ports
B.10. MBIST interface signal
D.1. Differences between issue B and issue C

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Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A30 November 2007First release for r0p0
Revision B04 April 2008First release for r1p0
Revision C19 December 2008First release for r2p0
Copyright © 2007, 2008 ARM Limited. All rights reserved.ARM DDI 0246C
Non-Confidential