AMBA Level 2 Cache Controller (L2C-310) Technical Reference ManualRevision: r3p0
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3.1.1. Initialization sequence

Caution

At boot time you must perform a Secure write to the Invalidate by Way, offset 0x77C, to invalidate all entries in the cache.

As an example, a typical cache controller start-up programming sequence consists of the following register operations:

  1. Write to the Auxiliary, Tag RAM Latency, Data RAM Latency, Prefetch, and Power Control registers using a read-modify-write to set up global configurations:

    • associativity, Way Size

    • latencies for RAM accesses

    • allocation policy

    • prefetch and power capabilities.

  2. Secure write to the Invalidate by Way, offset 0x77C, to invalidate all entries in cache:

    • Write 0xFFFF to 0x77C

    • Poll cache maintenance register until invalidate operation is complete.

  3. Write to the Lockdown D and Lockdown I Register 9 if required.

  4. Write to interrupt clear register to clear any residual raw interrupts set.

  5. Write to the Interrupt Mask Register if you want to enable interrupts.

  6. Write to Control Register 1 with the LSB set to 1 to enable the cache.

If you write to the Auxiliary, Tag RAM Latency, or Data RAM Latency Control Register with the L2 cache enabled, this results in a SLVERR. You must disable the L2 cache by writing to the Control Register 1 before writing to the Auxiliary, Tag RAM Latency, or Data RAM Latency Control Register.

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