AMBA Level 2 Cache Controller (L2C-310) Technical Reference Manual: 3.3.4. Auxiliary Control Register

3.3.4. Auxiliary Control Register

The reg1_aux_control Register characteristics are:

Purpose

Configures:

cache behavior
event monitoring
way size
associativity.

Usage constraints

The register must be written to using a secure access and with its reserved bits preserved. It can be read using either a secure or a NS access. If you write to this register with a NS access, it results in a write response with a DECERR response, and the register is not updated. Writing to this register with the L2 cache enabled, that is, bit[0] of L2 Control Register set to 1, results in a SLVERR. The DECERR response has priority over SLVERR.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.2.

Figure 3.4 shows the reg1_aux_control Register bit assignments.

Figure 3.4. reg1_aux_control Register bit assignments

Table 3.6 shows the reg1_aux_control Register bit assignments.

Table 3.6. reg1_aux_control Register bit assignments

Bits	Field	Description
[31]	Reserved	SBZ/RAZ
[30]	Early BRESP enable	0 = Early BRESP disabled. This is the default. 1 = Early BRESP enabled. See Early write response.
[29]	Instruction prefetch enable	0 = Instruction prefetching disabled. This is the default. 1 = Instruction prefetching enabled. See Prefetch Control Register.
[28]	Data prefetch enable	0 = Data prefetching disabled. This is the default. 1 = Data prefetching enabled. See Prefetch Control Register.
[27]	Non-secure interrupt access control	0 = Interrupt Clear, `0x220`, and Interrupt Mask, `0x214`, can only be modified or read with secure accesses. This is the default. 1 = Interrupt Clear, `0x220`, and Interrupt Mask, `0x214`, can be modified or read with secure or non-secure accesses.
[26]	Non-secure lockdown enable	0 = Lockdown registers cannot be modified using non-secure accesses. This is the default. 1 = Non-secure accesses can write to the lockdown registers.
[25]	Cache replacement policy	0 = pseudo-random replacement using lfsr. 1 = round-robin replacement. This is the default. See Replacement strategy.
[24:23]	Force write allocate	b00 = Use AWCACHE attributes for WA. This is the default. b01 = Force no allocate, set WA bit always 0. b10 = Override AWCACHE attributes, set WA bit always 1, all cacheable write misses become write allocated. b11 = Internally mapped to 00. See Cache operation for more information.
[22]	Shared attribute override enable	0 = Treats shared accesses as specified in Shareable attribute. This is the default. 1 = Shared attribute internally ignored.
[21]	Parity enable	0 = Disabled. This is the default. 1 = Enabled.
[20]	Event monitor bus enable	0 = Disabled. This is the default. 1 = Enabled.
[19:17]	Way-size^[a]	b000 = Reserved, internally mapped to 16KB. b001 = 16KB. b010 = 32KB. b011 = 64KB. b100 = 128KB. b101 = 256KB. b110 = 512KB. b111 = Reserved, internally mapped to 512 KB.
[16]	Associativity^[b]	0 = 8-way. 1 = 16-way.
[15:14]	Reserved	SBZ/RAZ
[13]	Shared Attribute Invalidate Enable	0 = Shared invalidate behavior disabled. This is the default. 1 = Shared invalidate behavior enabled, if Shared Attribute Override Enable bit not set. See Shareable attribute.
[12]	Exclusive cache configuration	0 = Disabled. This is the default. 1 = Enabled, see Exclusive cache configuration.
[11]	Store buffer device limitation Enable	0 = Store buffer device limitation disabled. Device writes can take all slots in store buffer. This is the default. 1= Store buffer device limitation enabled. Device writes cannot take all slots in store buffer when connected to the Cortex-A9 MPCore processor. There is always one available slot to service Normal Memory.
[10]	High Priority for SO and Dev Reads Enable	0 = Strongly Ordered and Device reads have lower priority than cacheable accesses when arbitrated in the L2CC (L2C-310) master ports. This is the default. 1 = Strongly Ordered and Device reads get the highest priority when arbitrated in the L2CC (L2C-310) master ports.
[9:1]	Reserved	SBZ/RAZ
[0]	Full Line of Zero Enable	0 = Full line of write zero behavior disabled. This is the default. 1 = Full line of write zero behavior Enabled. See Full line of zero write.
^[a]The default value of the way size depends on how the external WAYSIZE pins are tied. ^[b]The default value of the associativity depends on how the external ASSOCIATIVITY pin is tied, and how the RTL is configured.

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