3.3.14. Prefetch Control Register

The Prefetch Control Register characteristics are:

Purpose

Enables prefetch-related features that can improve system performance.

Usage constraints

This register has both read-only, non-secure, and read and write, secure, permissions. Any secure or non-secure access can read this register. Only a secure access can write to this register. If a non-secure access attempts to write to this register, the register issues a DECERR response and does not update.

Note

You must preserve the reserved bits when you write to this register.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 3.2.

Figure 3.16 shows the Prefetch Control Register bit assignments.

Figure 3.16. Prefetch Control Register bit assignments


Table 3.39 shows the register bit assignments.

Table 3.39. Prefetch Control Register bit assignments

BitsFieldDescription
[31]ReservedSBZ/RAZ
[30]Double linefill enable

You can set the following options for this register bit:

0

The L2CC always issues 4x64-bit read bursts to L3 on reads that miss in the L2 cache. This is the default.

1

The L2CC issues 8x64-bit read bursts to L3 on reads that miss in the L2 cache.

[29]Instruction prefetch enable[a]

You can set the following options for this register bit:

0

Instruction prefetching disabled. This is the default.

1

Instruction prefetching enabled.

[28]Data prefetch enable[a]

You can set the following options for this register bit:

0

Data prefetching disabled. This is the default.

1

Data prefetching enabled.

[27:25]ReservedSBZ/RAZ
[24]Prefetch drop enable

You can set the following options for this register bit:

0

The L2CC does not discard prefetch reads issued to L3. This is the default.

1

The L2CC discards prefetch reads issued to L3 when there is a resource conflict with explicit reads.

[23]Incr double Linefill enable

You can set the following options for this register bit:

0

The L2CC does not issue INCR 8x64-bit read bursts to L3 on reads that miss in the L2 cache. This is the default.

1

The L2CC can issue INCR 8x64-bit read bursts to L3 on reads that miss in the L2 cache.

[22]ReservedSBZ/RAZ
[21]Not same ID on exclusive sequence enable

You can set the following options for this register bit:

0

Read and write portions of a non-cacheable exclusive sequence have the same AXI ID when issued to L3. This is the default.

1

Read and write portions of a non-cacheable exclusive sequence do not have the same AXI ID when issued to L3.

[20:5]ReservedSBZ/RAZ
[4:0]Prefetch offsetDefault = b00000.

[a] You can access these bits by using both the Auxiliary Control Register, see Auxiliary Control Register, and the Prefetch Control Register. You cannot modify the Auxiliary Control register when the L2 cache is enabled. You can modify the Prefetch Control Register in all conditions.


See AXI locked and exclusive accesses for more information.

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