In the case of a non-cacheable transfer, the access is forwarded to L3 memory through the master ports and is marked as locked.

In the case of cacheable transfers, a cache lookup is always performed. In the case of a cache miss, a linefill, non-locked, is requested on the master side. Write accesses always cause non-locked writes on the master side.

When a slave is performing a locked sequence, cacheable or not, the other slave is stopped from accepting more transfers. A locked transaction is stalled until all buffers are empty, including the store buffer.

The processor must ensure that there is only one outstanding transaction across the read and write channels during a locked sequence.

If multiple locked transfers come in at the same time, they are permitted to proceed in a certain priority. The priority for locked transfers is that S0 takes priority over S1.

The cache controller supports cacheable and non-cacheable exclusive accesses but does not provide an exclusive monitor. The system integrator must implement external exclusive monitors as follows, so that the EXOKAY response can be returned:

The monitor on the slave side must be aware of the cache controller internal status, such as the shared override bit, to determine which accesses are cacheable and which are not.

The AXI specification requires that control signals in the read and write portions of an exclusive sequence must be identical. This includes the AXI ID. However, the L2C-310 enables you to issue different AXI IDs between the read and write portions of a non-cacheable exclusive sequence when the accesses are sent to L3. If the exclusive monitor located in the L3 memory system supports this behavior, this enables you to maximize the performance during the exclusive sequence.