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This section describes:
The text and figures in this section apply to both tag RAM and data RAM.
Clock enables can be used if the RAMs are run at a slower frequency than the cache controller logic. Only integer ratios are supported. With this scheme, the tag RAM and the data RAM can run at different frequencies. Table 2.20 shows the RAM clock enables and their functions.
Table 2.20. RAM clock enables
| Signal | Function |
|---|---|
| TAGCLKEN | Clock enable input that enables the tag RAM interface in the cache controller to communicate with the tag RAM clocked at a slower frequency. |
| TAGCLKOUTEN | Clock enable output used to gate the clock to the tag RAM to save power. Use this signal when you run the tag RAM at a slower frequency than the cache controller logic. |
| TAGCLKOUT | Gated version of CLK that is only enabled when the tag RAM is accessed. Use this clock if you run the tag RAM and the cache controller logic at the same frequency. |
| DATACLKEN | Clock enable input that enables the data RAM interface in the cache controller to communicate with the data RAM clocked at a slower frequency. |
| DATACLKOUTEN | Clock enable output used to gate the clock to the data RAM to save power. Use this signal when you run the data RAM at a slower frequency than the cache controller logic. When you implement banking, four clock enable outputs exist, one for each bank. |
| DATACLKOUT | Gated version of CLK that is only enabled when the data RAM is accessed. Use this clock you run the data RAM and the cache controller logic at the same frequency. When you implement banking, four clock outputs exist, one for each bank. |
Figure 2.16 shows an example of the tag RAM running at half the frequency compared to the cache controller.
Figure 2.17 shows how the different clock gates used in the tag RAM clocking can be implemented.
The implementer of the RAM array must also be the one that implements the clock gating cell that outputs TAGCLK in Figure 2.17.
Programmable RAM latencies enable the cache controller to manage RAMs requiring several clock cycles for dealing with accesses. For each RAM, there are three programmable latencies:
setup
read access
write access.
See Tag and Data RAM Latency Control Registers.
Setup latency is the number of cycles that the RAM control
signals remain valid prior to the RAM clock edge. Figure 2.18 shows a timing
diagram where the tag RAM setup latency has been programmed with
the value 0x1.
Read access latency is the number of cycles taken by the read
data to become valid after the RAM clock edge. Figure 2.19 shows a timing
diagram where the tag RAM read access latency has been programmed
with the value 0x1.
Write access latency is the minimum number of cycles between
a RAM clock edge for a write access and the next RAM clock edge
corresponding to another access, read or write. Figure 2.20 shows a timing
diagram where the tag RAM write access latency has been programmed
with the value 0x1.
The programmed RAM latency values refer to the actual clock driving the RAMs, that is, the slow clock if the RAMs are clocked slower than the cache controller.
When you implement banking for the data RAM, the programmed data RAM latencies apply to all four banks. Implement banking on the data RAM if you want to reduce overall access latency. Data RAM banking has no effect on the setup latency.
| Copyright © 2007-2009 ARM. All rights reserved. | ARM DDI 0246D |
| Non-Confidential | |
| PDF version | |
| Home > Functional Overview > RAM interfaces > RAM clocking and latencies |