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The ARUSERSx[0] and AWUSERSx[0] signals affect transactions. Typically, these signals are driven by ARM processors and reflect the shareable attribute as defined in the ARM v6 and v7 architecture.
Shared only applies to Normal Memory outer non-cacheable transactions, where ARCACHESx or AWCACHESx = 0010 or 0011. For other values of ARCACHESx and AWCACHESx, the shareable attribute is ignored.
The default behavior of the cache controller with respect to the shareable attribute is to transform Normal Memory Non-cacheable transactions into:
cacheable no allocate for reads
write through no write allocate for writes.
You can change this default shared behavior by setting the Shareable attribute Invalidate Enable bit in the Auxiliary Control Register, bit[13]. When you set this bit, writes targeting a full cache line, for example 4x64-bit bursts with all strobes active, and hitting in the L2 cache invalidate the corresponding cache line and are forwarded to L3. Other cases are identical to the default shared behavior.
The Shareable attribute Invalidate Enable bit can cause the invalidation of L2 cache lines even if they are dirty. So you must only enable this bit in systems supporting this behavior. When you set this bit in such systems, all non-cacheable writes marked as shared must be 4x64-bit bursts targeting a full cache line. Otherwise, the behavior might be unpredictable.
Both of these shared behaviors are disabled if you set the Shareable attribute Override Enable bit in the Auxiliary Control Register, bit[22].
Dynamically changing the Shareable attribute Override Enable bit without flushing the cache could cause a hazard where incorrect data could be evicted causing more recent data in L3 to be overwritten.
The behavior of the L2CC (L2C-310) with respect to the shareable attribute is different from the L220 Level 2 cache controller. Take care when moving from an L220 based system to a system implementing L2CC (L2C-310), because the shareable attribute and the Shared Attribute Override Enable bit affects the point of coherency of such systems.
| Copyright © 2007-2009 ARM. All rights reserved. | ARM DDI 0246D |
| Non-Confidential | |
| PDF version | |
| Home > Functional Overview > Cache operation > Shareable attribute |