AMBA Level 2 Cache Controller (L2C-310) Technical Reference ManualRevision: r3p0
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A.4.2. Tag RAM interface

Table A.8 shows the tag RAM interface signals.

Table A.8. Tag RAM interface

SignalTypeDescription
TAGADDR[13:0]OutputTag RAM address

TAGCS[15:0][a]

TAGCS[7:0][b]

OutputTag RAM chip selects
TAGEN[20:0]OutputTag RAM write enable
TAGLEN[c]OutputTag RAM lock write enable

TAGERR[15:0][a]

TAGERR[7:0][b]

InputTag RAM error
TAGnRWOutputTag RAM write control

TAGPRD[15:0][a][d]

TAGPRD[7:0][b][d]

InputTag RAM parity read data

TAGLRD[15:0][a][c]

TAGLRD[7:0][b][c]

InputTag RAM lock read data
TAGPEN[d]OutputTag RAM parity write enable
TAGPWD[d]OutputTag RAM parity write data
TAGLWD[c]OutputTag RAM lock write data
TAGRD0[20:0]InputTag RAM 0 read data
TAGRD1[20:0]InputTag RAM 1 read data
TAGRD2[20:0]InputTag RAM 2 read data
TAGRD3[20:0]InputTag RAM 3 read data
TAGRD4[20:0]InputTag RAM 4 read data
TAGRD5[20:0]InputTag RAM 5 read data
TAGRD6[20:0]InputTag RAM 6 read data
TAGRD7[20:0]InputTag RAM 7 read data
TAGRD8[20:0][e]InputTag RAM 8 read data
TAGRD9[20:0][e]InputTag RAM 9 read data
TAGRD10[20:0][e]InputTag RAM 10 read data
TAGRD11[20:0][e]InputTag RAM 11 read data
TAGRD12[20:0][e]InputTag RAM 12 read data
TAGRD13[20:0][e]InputTag RAM 13 read data
TAGRD14[20:0][e]InputTag RAM 14 read data
TAGRD15[20:0][e]InputTag RAM 15 read data
TAGWAITInputTag RAM wait
TAGWD[20:0]OutputTag RAM write data

[a] For a 16-way implementation.

[b] For an 8-way implementation.

[c] Optional. Only present if pl310_LOCKDOWN_BY_LINE is defined.

[d] Optional. Only present if pl310_PARITY is defined.

[e] Only present for a 16-way implementation.


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