| Copyright © 2007-2009 ARM. All rights reserved. | ARM DDI 0246D |
| Non-Confidential | |
 PDF version | |
| Home > Signal Descriptions > Slave and master ports |
| |||
| Home > Signal Descriptions > Slave and master ports | |||
The slave and master ports are described in the following sections:
Signals AWSIZES0/1[2], WIDS0/1[5:0], and ARSIZES0/1[2] are not used internally.
| Copyright © 2007-2009 ARM. All rights reserved. | ARM DDI 0246D |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > Slave and master ports |