B.4. Master port 0 input and output signal timing parameters
Table B.4 shows
the master port 0 input and output signal timing parameters.
Table B.4. Master port 0 inputs and outputs
| Port name | Type | Maximum constraint |
|---|
| ARADDRM0[31:0] | Output | 70% |
| ARBURSTM0[1:0] | Output | 70% |
| ARCACHEM0[3:0] | Output | 70% |
| ARIDM0[7:0] | Output | 70% |
| ARLENM0[3:0] | Output | 70% |
| ARLOCKM0[1:0] | Output | 70% |
| ARPROTM0[2:0] | Output | 70% |
| ARREADYM0 | Input | 50% |
| ARSIZEM0[2:0] | Output | 70% |
| ARVALIDM0 | Output | 70% |
| AWADDRM0[31:0] | Output | 70% |
| AWBURSTM0[1:0] | Output | 70% |
| AWCACHEM0[3:0] | Output | 70% |
| AWIDM0[7:0] | Output | 70% |
| AWLENM0[3:0] | Output | 70% |
| AWLOCKM0[1:0] | Output | 70% |
| AWPROTM0[2:0] | Output | 70% |
| AWREADYM0 | Input | 50% |
| AWSIZEM0[2:0] | Output | 70% |
| AWVALIDM0 | Output | 70% |
| BIDM0[7:0] | Input | 50% |
| BREADYM0 | Output | 70% |
| BRESPM0[1:0] | Input | 50% |
| BVALIDM0 | Input | 50% |
| INCLKENM0 | Input | 30% |
| OUTCLKENM0 | Output | 30% |
| RDATAM0[63:0] | Input | 50% |
| RIDM0[7:0] | Input | 50% |
| RLASTM0 | Input | 50% |
| RREADYM0 | Output | 70% |
| RRESPM0[1:0] | Input | 50% |
| RVALIDM0 | Input | 50% |
| WDATAM0[63:0] | Output | 70% |
| WIDM0[7:0] | Output | 70% |
| WLASTM0 | Output | 70% |
| WREADYM0 | Input | 50% |
| WSTRBM0[7:0] | Output | 70% |
| WVALIDM0 | Output | 70% |
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