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Table B.8 shows the event monitor input and output signal timing parameters.
Table B.8. Event monitor inputs and outputs
| Port name | Type | Maximum constraint |
|---|---|---|
| CO | Output | 70% |
| DRHIT | Output | 70% |
| DRREQ | Output | 70% |
| DWHIT | Output | 70% |
| DWREQ | Output | 70% |
| DWTREQ | Output | 70% |
| EPFALLOC | Output | 70% |
| EPFHIT | Output | 70% |
| EPFRCVDS0 | Output | 70% |
| EPFRCVDS1 | Output | 70% |
| IPFALLOC | Output | 70% |
| IRHIT | Output | 70% |
| IRREQ | Output | 70% |
| SRCONFS0 | Output | 70% |
| SRCONFS1 | Output | 70% |
| SRRCVDS0 | Output | 70% |
| SRRCVDS1 | Output | 70% |
| SPNIDEN | Input | 70% |
| WA | Output | 70% |
| Copyright © 2007-2009 ARM. All rights reserved. | ARM DDI 0246D |
| Non-Confidential | |
| PDF version | |
| Home > AC Parameters > Event monitor input and output signal timing parameters |