AMBA Level 2 Cache Controller (L2C-310) Technical Reference ManualRevision: r3p0
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B.9. MBIST interface input and output signal timing parameters

Table B.10 shows the MBIST interface input and output signal timing parameters.

Table B.10. MBIST interface signal inputs and outputs

Port nameTypeMaximum constraint
MBISTADDR[18:0]Input70%
MBISTCE[17:0]Input70%
MBISTDCTL[19:0]Output70%
MBISTDIN[63:0]Input70%
MBISTWEInput70%
MBISTONInput30%
MBISTDOUT[63:0]Output50%

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