AMBA Level 2 Cache Controller (L2C-310) Technical Reference Manual: 2.3.1. Cache attributes

2.3.1. Cache attributes

Table 2.16 describes the AWCACHE[3:0] and ARCACHE[3:0] signals as the AMBA AXI Protocol Specification defines, and the ARMv6 and ARMv7 equivalent meaning. Table 2.16 does not show AXI locked and exclusive accesses.

Table 2.16. AWCACHE and ARCACHE definitions

AWCACHE/ARCACHE				AXI meaning	ARMv6 and ARMv7 equivalent
WA	RA	C	B	AXI meaning	ARMv6 and ARMv7 equivalent
0	0	0	0	Non-cacheable, non-bufferable	Strongly ordered
0	0	0	1	Bufferable only	Device
0	0	1	0	Cacheable but do not allocate	Outer non-cacheable
0	0	1	1	Cacheable and bufferable, do not allocate	Outer non-cacheable
0	1	1	0	Cacheable write-through, allocate on read	Outer write-through, no allocate on write
0	1	1	1	Cacheable write-back, allocate on read	Outer write-back, no allocate on write
1	0	1	0	Cacheable write-through, allocate on write	-
1	0	1	1	Cacheable write-back, allocate on write	-
1	1	1	0	Cacheable write-through, allocate on both read and write	-
1	1	1	1	Cacheable write-back, allocate on both read and write	Outer write-back, write allocate

Note

The shareable attribute AW/RUSERSx[0] is not described in this table. Shareable attribute describes its behavior.
The cache controller supports all AXI cache attributes, even if the processor does not use all of them.
If the cache controller receives cacheable fixed transactions, AWBURST or ARBURSTSx = 00, the results are unpredictable.

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