AMBA Level 2 Cache Controller (L2C-310) Technical Reference ManualRevision: r3p0
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2.3.6. Cache lockdown

You can use these lockdown mechanisms in the L2CC (L2C-310):

You can use the lockdown by line and the lockdown by way at the same time. You can also use the lockdown by line and the lockdown by master at the same time. But lockdown by master and lockdown by way are exclusive because lockdown by way is a subset of the lockdown by master.

The Lockdown by master feature is optional. You can only implement it if you define the parameter pl310_LOCKDOWN_BY_MASTER, see Cache configurability.

Lockdown by line

This feature is optional. You can only implement it if you define the parameter pl310_LOCKDOWN_BY_LINE, see Cache configurability.

When enabled during a period of time, all newly allocated cache lines get marked as locked. The controller then considers them as locked and does not naturally evict them. You enable it by setting bit [0] of the Lockdown by Line Enable Register, see Table 3.18. The optional bit [21] of the tag RAM shows the locked status of each cache line.

Note

An example of when you might enable the lockdown by line feature is during the time when you load a critical piece of software code into the L2 cache.

The Unlock All Lines background operation enables you to unlock all lines marked as locked by the Lockdown by Line mechanism. You can check the status of this operation by reading the Unlock All Lines register, see Table 3.19.

Lockdown by way

The 32-bit ADDR cache address consists of the following fields:

< TAG > < INDEX > < WORD > < BYTE >.

When a cache lookup occurs, the Index defines where to look in the cache ways. The number of ways defines the number of locations with the same Index. This is called a Set. Therefore a 16-way set associative cache has 16 locations where an address with INDEX (A) can exist.

The Lockdown format C, as the ARM Architecture Reference Manual describes, provides a method to restrict the replacement algorithm used for allocations of cache lines within a Set.

This method enables you to:

  • fetch code or load data into the L2 cache

  • protect it from being evicted.

You can also use this method to reduce cache pollution.

You can use two registers to control this mechanism, see Table 3.20 and Table 3.21.

Lockdown by master

The Lockdown by master feature is a superset of the Lockdown by way feature. It enables multiple masters to share the L2 cache and makes the L2 cache behave as though these masters have dedicated smaller L2 caches.

This feature enables you to reserve ways of the L2 cache to specific L1 masters that the ID on the AR/WUSERSx[7:5], x=0, 1, signals identify.

You can use sixteen registers for controlling this mechanism. See the tables from Table 3.20 to Table 3.35.

System including four Cortex-A9 MPCore processors and L2CC (L2C-310) and System including one Cortex-A9 MPCore processor with ACP and L2CC (L2C-310) describe two examples of a system that use the lockdown by master. They show you how to drive AR/WUSERSx[7:5] signals and program the relevant registers.

System including four Cortex-A9 MPCore processors and L2CC (L2C-310)

Figure 2.5 shows a system where a Cortex-A9 cluster with four CPUs drives the L2CC (L2C-310).

Figure 2.5. Driven by cortex a9 cluster with 4 CPUs


If you implement the L2CC (L2C-310) with a 16-way associativity, the lockdown by master feature enables you to reserve four ways for each CPU. If you want to reserve four ways for each CPU, they are for allocations only. All CPUs have access to all of the ways for lookups and hits.

For this system, you can drive the AR/WUSERSx[7:5] signals as follows:

AR/WUSERSx[7:5] = {1'b0, AR/WIDMx[1:0]}.

Note

AR/WIDMx[1:0] are the AXI ID bits that the Cortex-A9 cluster drives, see the Cortex-A9 Technical Reference Manual.

Table 2.17 shows how you can program the lockdown registers.

Table 2.17. MP4 system lockdown register definitions

RegisterOffsetValue
Data Lockdown 0[a]0x9000x0000FFF0
Instruction Lockdown 00x9040x0000FFF0
Data Lockdown 10x9080x0000FF0F
Instruction Lockdown 10x90C0x0000FF0F
Data Lockdown 20x9100x0000F0FF
Instruction Lockdown 20x9140x0000F0FF
Data Lockdown 30x9180x00000FFF
Instruction Lockdown 3[b] 0x91C0x00000FFF
All other Lockdown registersox920 - 0x93Cdefault

[a] Use when AR/WUSERSx[7:5] = 000, transactions from CPU0, and AR/WPROTSx[2] = 0.

[b] Use when AR/WUSERSx[7:5] = 011, transactions from CPU3, and AR/WPROTSx[2] = 1.


This configuration reserves:

  • ways [0:3] for CPU0

  • ways [4:7] for CPU1

  • ways [8:11] for CPU2

  • ways [12:15] for CPU3.

System including one Cortex-A9 MPCore processor with ACP and L2CC (L2C-310)

Figure 2.6 shows a system where the Cortex-A9 cluster has only one CPU and the Accelerator Coherence Port (ACP) drives the L2CC (L2C-310).

Figure 2.6. Driven by cortex a9 cluster with 1 CPU and ACP


If you implement the L2CC (L2C-310) with 8-way associativity, the lockdown by master feature enables you to reserve four ways for the CPU and the other four ways for the master to drive the ACP.

For this system you can drive the AR/WUSERSx[7:5] signals as follows:

  • AR/WUSERSx[7:5] = {2'b00, AR/WIDMx[2]}.

Note

AR/WIDMx are the AXI ID bits that the Cortex-A9 cluster drives, see the Cortex-A9 Technical Reference Manual.

Table 2.18 shows how you can program the lockdown registers.

Table 2.18. MPI plus APC system lockdown register definitions.

RegisterOffsetValue
Data Lockdown 0[a]0x9000x000000F0
Instruction Lockdown 00x9040x000000F0
Data Lockdown 10x9080x0000000F
Instruction Lockdown 1[b]0x90C0x0000000F
All other Lockdown registersox910 - 0x93Cdefault

[a] use when AR/WUSERSx[7:5] = 000, transactions from CPU, and AR/WPROTSx[2] = 0.

[b] use when AR/WUSERSx[7:5] = 001, transactions from ACP, and AR/WPROTSx[2] = 1.


When you have programmed the registers, and the cache controller drives AR/WUSERSx[7:5] as Lockdown by way shows, the cache controller reserves:

  • ways [3:0] for the Cortex-A9 CPU

  • ways [7:4] for the ACP.

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