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Table B.4 shows the Data RAM input and output signal timing parameters.
Table B.4. Data RAM inputs and outputs
| Port name | Type | Maximum constraint |
|---|---|---|
| DATAADDR[17:0][a] | Output | 70% |
| DATAADDR[16:0][b] | ||
| DATAADDR[15:0][c] | ||
| DATAADDR[14:0][d] | ||
| DATACLKEN | Input | 30% |
| DATACLKOUT | Output | 50% |
| DATACLKOUTEN | Output | 50% |
| DATACS[e] | Output | 70% |
| DATAEN[31:0] | Output | 70% |
| DATAERR[e] | Input | 50% |
| DATAnRW | Output | 70% |
| DATAPEN[31:0] | Output | 70% |
| DATAPnRW | Output | 70% |
| DATAPRD[31:0][f] | Input | 50% |
| DATAPWD[31:0][f] | Output | 70% |
| DATARD[255:0] | Input | 50% |
| DATAWAIT | Input | 30% |
| DATAWD[255:0] | Output | 70% |
[a] For a 16-way implementation, without banking. [b] For an 8-way implementation, without banking. [c] For a 16-way implementation, with banking. [d] For an 8-way implementation, with banking. [e] Without banking. [f] Optional. Only present if | ||
| Copyright © 2007-2010 ARM. All rights reserved. | ARM DDI 0246E |
| Non-Confidential | |
| PDF version | |
| Home > AC Parameters > RAMs signal timing parameters > Data RAM input and output signal timing parameters |