The base address of the cache controller is not fixed, and can be different for any particular system implementation. However, the offset of any particular register from the base address is fixed.

The cache controller is controlled through a set of memory-mapped registers that occupy a re-locatable 4KB of memory. You must define this region with Strongly Ordered or Device memory attributes in the L1 page tables. You can access the registers through direct address decoding in the slave ports. REGFILEBASE[31:12] provides the base address for these ports.

Reserved or unused address locations must not be accessed because this can result in unpredictable behavior of the device.

You must preserve the reserved bits in all registers otherwise unpredictable behavior of the device might occur.

All registers support read and write accesses unless otherwise stated in the relevant text. A write updates the contents of a register and a read returns the contents of the register.

All writes to registers automatically perform an initial Cache Sync operation before proceeding.

Bits [1:0] of the address must be zero, otherwise a SLVERR response is returned.

The burst length must be equal to zero, otherwise a SLVERR response is returned.

Only 32-bit accesses are permitted, otherwise a SLVERR response is returned.

Exclusive accesses are not permitted. A SLVERR response is returned.

The cache controller ignores the write strobes and always considers the write strobes to be 0x0F or 0xF0 depending on the offset. When the cache controller accesses the registers it does not support sparse write strobes.

Any write to a writable register returns SLVERR while a background operation is in progress.