| ASSOCIATIVITY | Input | Associativity for Auxiliary Control Register.
See Auxiliary Control Register. |
| CACHEID[5:0] | Input | Cache controller cache ID. |
| CFGADDRFILTEN[] | Input | Address filtering Enable out of reset. |
| CFGADDRFILTEND[11:0][] | Input | Address filtering End Address out of reset. |
| CFGADDRFILTSTART[11:0][] | Input | Address filtering Start Address out of reset. |
| CFGBIGEND | Input | Big-endian mode for accessing configuration
registers out of reset. |
| DATAREADLAT[2:0] | Output | Read access latency for Data RAM. |
| DATASETUPLAT[2:0] | Output | Setup latency for Data RAM. |
| DATAWRITELAT[2:0] | Output | Write access latency for Data RAM. |
| REGFILEBASE[19:0] | Input | Base address for accessing configuration registers. |
| SE | Input | DFT test enable, held HIGH during serial shift
of scan chains and LOW for capture. |
| TAGREADLAT[2:0] | Output | Read access latency for tag RAM. |
| TAGSETUPLAT[2:0] | Output | Setup latency for tag RAM. |
| TAGWRITELAT[2:0] | Output | Write access latency for tag RAM. |
| WAYSIZE[2:0] | Input | Size of ways for Auxiliary Control Register.
See Auxiliary Control Register. |
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