Table A.4 shows
the master port 0 signals.
Table A.4. Master port 0 signals
| Signal | Type | Description |
|---|
| ARADDRM0[31:0] | Output | Address bus |
| ARBURSTM0[1:0] | Output | Burst type |
| ARCACHEM0[3:0] | Output | Cache information |
| ARIDM0[`pl310_AXI_ID_MAX+2:0] | Output | Address ID |
| ARLENM0[3:0] | Output | Burst length |
| ARLOCKM0[1:0] | Output | Lock type |
| ARPROTM0[2:0] | Output | Protection information |
| ARREADYM0 | Input | Address accepted |
| ARSIZEM0[2:0] | Output | Burst size |
| ARUSERM0[] | Output | ID indication of L1 originating transaction |
| ARVALIDM0 | Output | Address valid |
| AWADDRM0[31:0] | Output | Address bus |
| AWBURSTM0[1:0] | Output | Burst type |
| AWCACHEM0[3:0] | Output | Cache information |
| AWIDM0[`pl310_AXI_ID_MAX+2:0] | Output | Address ID |
| AWLENM0[3:0] | Output | Burst length |
| AWLOCKM0[1:0] | Output | Lock type |
| AWPROTM0[2:0] | Output | Protection information |
| AWREADYM0 | Input | Address accepted |
| AWSIZEM0[2:0] | Output | Burst size |
| AWUSERM0[] | Output | ID indication of L1 originating transaction |
| AWVALIDM0 | Output | Address valid |
| BIDM0[`pl310_AXI_ID_MAX+2:0] | Input | Write ID |
| BREADYM0 | Output | Write response accepted |
| BRESPM0[1:0] | Input | Write response |
| BVALIDM0 | Input | Write response valid |
| RDATAM0[63:0] | Input | Read data bus |
| RIDM0[`pl310_AXI_ID_MAX+2:0] | Input | Read ID |
| RLASTM0 | Input | Read last transfer |
| RREADYM0 | Output | Read accepted |
| RRESPM0[1:0] | Input | Read response |
| RVALIDM0 | Input | Read data valid |
| WDATAM0[63:0] | Output | Write data bus |
| WIDM0[`pl310_AXI_ID_MAX+2:0] | Output | Write ID |
| WLASTM0 | Output | Write last transfer |
| WREADYM0 | Input | Write data accepted |
| WSTRBM0[7:0] | Output | Write strobes |
| WVALIDM0 | Output | Write data valid |
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