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Table A.8 shows the cache interrupt signals.
Table A.8. Cache interrupt signals
| Signal | Type | Description |
|---|---|---|
| DECERRINTR | Output | Decode error received on master port from L3 |
| ECNTRINTR | Output | Event Counter Overflow/Increment |
| ERRRDINTR | Output | Error on L2 data RAM read |
| ERRRTINTR | Output | Error on L2 tag RAM read |
| ERRWDINTR | Output | Error on L2 data RAM write |
| ERRWTINTR | Output | Error on L2 data RAM write |
| L2CCINTR | Output | Combined Interrupt Output |
| PARRDINTR | Output | Parity error on L2 data RAM read |
| PARRTINTR | Output | Parity error on L2 tag RAM read |
| SLVERRINTR | Output | Slave error received on master port from L3 |
| Copyright © 2007-2010 ARM. All rights reserved. | ARM DDI 0246E |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > Cache interrupt |