CoreLink Level 2 Cache Controller L2C-310 Technical Reference ManualRevision: r3p2
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A.4.1. Data RAM interface

Data RAM interfaceTable A.5 shows the data RAM interface signals.

Table A.5. Data RAM interface signals

SignalTypeDescription

DATAADDR[17:0][a]

DATAADDR[16:0][b]

DATAADDR[15:0][c]

DATAADDR[14:0][d]

OutputData RAM address

DATACS[e]

DATACS[3:0][f]

OutputData RAM chip select
DATAEN[31:0]OutputData RAM byte write enables

DATAERR[e]

DATAERR[3:0][f]

InputData RAM error
DATAnRWOutputData RAM write control signal
DATAPRD[31:0][g]InputData RAM parity read data
DATAPWD[31:0][g]OutputData RAM parity write data
DATARD[255:0]InputData RAM read data
DATAWAITInputData RAM wait
DATAWD[255:0]OutputData RAM write data

[a] For a 16-way implementation, without banking.

[b] For an 8-way implementation, without banking.

[c] For a 16-way implementation, with banking.

[d] For an 8-way implementation, with banking.

[e] Without banking.

[f] With banking.

[g] Optional. Only present if pl310_PARITY is defined.


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