2.3.1. Cache attributes

Table 2.14 shows the AWCACHE[3:0] and ARCACHE[3:0] signals as the AMBA AXI Protocol Specification defines, and the ARMv6 and ARMv7 equivalent meaning. Table 2.14 does not show AXI locked and exclusive accesses.

Table 2.14. AWCACHE and ARCACHE definitions

AWCACHE and ARCACHEAXI meaningARMv6 and ARMv7 equivalent
WARACB
0000Non-cacheable, non-bufferableStrongly ordered
0001Bufferable onlyDevice
0010Cacheable but do not allocateOuter non-cacheable
0011Cacheable and bufferable, do not allocateOuter non-cacheable
0110Cacheable write-through, allocate on readOuter write-through, no allocate on write
0111Cacheable write-back, allocate on readOuter write-back, no allocate on write
1010Cacheable write-through, allocate on write-
1011Cacheable write-back, allocate on write-
1110Cacheable write-through, allocate on both read and write-
1111Cacheable write-back, allocate on both read and writeOuter write-back, write allocate

Note

  • This table does not describe the shareable attribute AyUSERSx[0], where y = R or W, and x = 0 or 1. Shareable attribute describes its behavior.

  • The cache controller supports all AXI cache attributes, even if the processor does not use all of them.

  • If the cache controller receives cacheable fixed transactions, AWBURST or ARBURSTSx = 00, the results are unpredictable.

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