The reset controller generates the power-on reset, nPOR, and AMBA reset signal, HRESETn.

The MPMCBIGENDIAN, MPMCSTCS1MW[1:0], and MPMCSTCS[3:0]POL signals are generated by registering the value of several inputs to the chip when the power-on reset goes inactive. These input signals are reused during normal operation.

The refresh controller can place the SDRAM memory devices into self-refresh mode by using the MPMCSREFREQ and MPMCSREFACK signals.

The clock select logic is used to select the various clocks. In TIC test mode, when MPMCTESTIN is HIGH, HCLK must operate at no more than 10MHz.