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The static memory chip selects can be configured on power-on reset by using tie-off signals.
The MPMC can be configured to boot from static memory.
Static memory chip select 1 contains additional functionality enabling it to be booted from. This chip select can be configured on power-on reset by setting a number of tie-offs. The value of these tie offs must not be changed during normal operation. The tie-offs enable the following to be configured:
polarity of the chip select
polarity of the byte lane strobe
memory width.
The power-on reset value of these signals can be determined by reading the appropriate fields in the MPMCStaticConfig1 Register. The tie-off values can be overridden by writing to the appropriate register field fields. The register then shows the updated value.
The tie-off signals are shown in Table 9.3.
Table 9.3. MPMCStaticConfig1 Register
| Configuration input signal | MPMCStaticConfig1 Register field | Configuration option |
|---|---|---|
| MPMCSTCS1MW[1:0] | Memory width (MW) | Chip select 1 data bus width:00 = 8-bit01 = 16-bit10 = 32-bit11 = reserved. |
| MPMCSTCS1PB | Byte lane state (PB) | Chip select 1 byte lane state:0 = nMPCSBLSOUT[3:0] signals are HIGH for reads and LOW for writes1 = nMPMCBLSOUT[3:0] signals are LOW for reads and LOW for writes. |
| MPMCSTCS1POL | Chip select polarity (PC) | Chip select 1 chip select polarity:0 = active LOW chip select1 = active HIGH chip select. |
If these tie-offs are not required these signals must be tied LOW.
Chip selects 0, 2, and 3 chip select polarity can be configured by the use of tie-offs to minimize the risk of bus clash. The value of these tie offs must not be changed while the MPMC is in normal operation. The power-on reset value of these signals can be determined by reading the appropriate chip select polarity (PC) field of the MPMCStaticConfig Register. The tie-off values can be overridden by writing to the chip select polarity (PC) field. The register then shows the updated value.
The tie-off signals are shown in Table 9.4.
Table 9.4. MPMCStaticConfig Register
| Configuration input signal | MPMCStaticConfig Register field | Configuration option |
|---|---|---|
| MPMCSTCS0POL | Chip select polarity (PC) | Chip select 0 chip select polarity:0 = active LOW chip select1 = active HIGH chip select. |
| MPMCSTCS2POL | Chip select polarity (PC) | Chip select 2 chip select polarity:0 = active LOW chip select1 = active HIGH chip select. |
| MPMCSTCS3POL | Chip select polarity (PC) | Chip select 3 chip select polarity:0 = active LOW chip select1 = active HIGH chip select. |
If these tie-offs are not required these signals must be tied LOW.
| Copyright © 2003 ARM Limited. All rights reserved. | ARM DDI 0269A |
| Non-Confidential | |
| PDF version | |
| Home > System Connectivity > On-chip signals > Static memory configuration |