ARM PrimeCell™ MultiPort Memory Controller (PL176) Technical Reference Manual 7.5. Transaction examples

7.5. Transaction examples

The following section provides examples of dynamic memory transactions, and contains the following subsections:

Single 64-bit read from SDR-SDRAM, row open
Single 64-bit write to SDR-SDRAM, row open
Burst 4 (INCR/INCR4/WRAP4) 64-bit read from 64-bit SDR-SDRAM, row open
Burst 4 (INCR/INCR4/WRAP4) 64-bit read from 64-bit SDR-SDRAM, bank precharged
Burst 4 (INCR/INCR4/WRAP4) 64-bit read from 64-bit SDR-SDRAM, different row open
Burst 4 (INCR/INCR4/WRAP4) 64-bit write to 64-bit SDR-SDRAM, row open
Burst 4 (INCR/INCR4/WRAP4) 64-bit write to 64-bit SDR-SDRAM, bank precharged
Burst 4 (INCR/INCR4/WRAP4) 64-bit write to 64-bit SDR-SDRAM, different row open
Two back-to-back burst 4 (INCR/INCR4/WRAP4) 64-bit read from 64-bit SDR-SDRAM, row open
Two back-to-back burst 4 (INCR/INCR4/WRAP4) 64-bit write to 64-bit SDR-SDRAM, row open.

Unless explicitly specified the following transactions use the parameters in Table 7.4 when:

Table 7.4. Transaction details

Parameter	Value
CAS latency	Two cycles
RAS latency	Two cycles
Precharge delay (tRP)	Two cycles
Memory controller state	Idle when request goes active
Pad interface scheme	Command delayed

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