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The following sections describe the pad interface connectivity for:
The static memory output signals, including NAND flash output signals, are generated using HCLK, and then combined with the dynamic memory and TIC output signals. See Figure 9.3 and Figure 9.6.
The static memory input signals are registered by HCLK, see Figure 9.2.
The TIC output signals are generated using HCLK, and then combined with the static memory and dynamic controller output signals, see Figure 9.3.
The TIC input signals are registered by HCLK, see Figure 9.2.
The SDR-SDRAM memory output signals are generated either using HCLK in the clock delayed pad interface methodology, or by MPMCHCLKDELAY clock using the command delayed pad interface methodology, see Pad interface methodology. The output signals are then combined with the static memory and TIC output signals. See Figure 9.3, Figure 9.4 and Figure 9.6.
The SDR-SDRAM memory input signals are first registered by the feedback clocks, MPMCFBCLKIN[7:0]. Depending on the edge of HCLK chosen to then register the read data, the read data is either:
captured straight onto the positive edge of HCLK
first captured on the negative of HCLK using nHCLK and then half a cycle later captured on the positive edge of HCLK.
See Figure 9.2.
The majority of the DDR-SDRAM memory output signals are generated either using HCLK in the clock delayed pad interface methodology, or by MPMCHCLKDELAY using the command delayed pad interface methodology. See Pad interface methodology. The output signals are then combined with the static memory and TIC output signals.
The write data, MPMCDATAOUT[31:0], and data mask, MPMCDQMOUT[7:0] signals are generated using the nHCLKX2 clock.
The output data strobe, MPMCDQSOUT[3:0] is generated using the HCLKX2 clock.
See Figure 9.3 to Figure 9.6.
The DDR-SDRAM memory input read data is provided at double the clock rate. The read data is therefore required to be captured on both edges of the data strobe. To resolve issues with instantiating negative edge d-types in the MPMC, in addition to the normal delayed data strobe signal, MPMCDQSIN[3:0], the MPMC requires an inverted data strobe signal nMPMCDQSIN[3:0], to capture the read data on the negative edge of the data strobe.
The first item of data is captured using the positive edge of the MPMCDQSIN[3:0] data strobe. The second item of data is captured using the positive edge of the nMPMCDQSIN[3:0] data strobe, half a cycle later. The first item of data captured on MPMCDQSIN[3:0] is registered on nMPMCDQSIN[3:0] after being captured in the MPMCDQSIN[3:0] domain. This means that both the first and second data items are in the nMPMCDQSIN[3:0] clock domain, making it easier to retime the read data back to the HCLK clock domain.
32-bit DDR-SDRAM devices have a single DQS connection, rather than one for each byte lane. This is because they are expected to be used in systems where the difference in delays between byte lanes is small. The single DQS on the memory device must be connected to all four DQS ports of the MPMC.
It is not recommended that 32-bit DDR-SDRAM devices are mixed with 8-bit or 16-bit DDR-SDRAM devices, because of the differences in DQS signals between the devices.
Depending on the edge of HCLK chosen to register the read data, the read data is either:
captured straight onto the positive edge of HCLK
first captured on the negative of HCLK using nHCLK and then half a cycle later captured on the positive edge of HCLK.
See Figure 9.2.
| Copyright © 2003 ARM Limited. All rights reserved. | ARM DDI 0269A |
| Non-Confidential | |
| PDF version | |
| Home > System Connectivity > On-chip signals > Pad interface connectivity |