SDRAM memory has several features to reduce power consumption:

JEDEC low-power SDRAM has several additional power reduction features compared to standard SDRAM.

One of the main ways that low-power SDRAM memory parts reduce power consumption over standard SDRAM parts is that they operate at a lower voltage and therefore consume less power than standard SDRAM memories.

Low-power SDRAM parts are designed to work in systems where power consumption is an important consideration, and where the clock frequency of the design might not be particularly high. These devices therefore generally enable lower CAS latency values, (for example CAS latency 1), compared to standard SDRAM.

Self-refresh mode power consumption is also reduced for low-power SDRAM devices. The devices enable the ambient temperature to be programmed into the device. The frequency of the self-refresh commands generated internally by the SDRAM are then scheduled accordingly. To use this functionality the ASIC must be able to measure the temperature. This temperature value must then be programmed into the SDRAM memory device (using the MPMC) before self-refresh mode is entered.

Low-power SDRAM provides a facility for selecting which memory banks to refresh in self-refresh mode. The memory banks that are not refreshed lose their data. When using this feature it is beneficial to use the bank, row, column (BRC) address-mapping scheme in the MPMC, so that a linear area of memory is not mapped over multiple SDRAM memory banks.

Finally low-power SDRAM memories also support deep sleep mode. In this mode the SDRAM memory is powered down. The content of the memory is lost.

DDR-SDRAM memory has the same power reduction as SDRAM.

DDR-SDRAM enables data to be transferred at double the rate of the clock, address and command signals. The memory interface uses half the number of data pins for a given bandwidth compared to SDR-SDRAM.

The DDR-SDRAM memory interface inherently consumes less power than standard SDR-SDRAM memory. However, when performing power analysis calculations comparing SDR and DDR memory systems you must bear in mind that DDR memory requires a differential external memory clock, and a Delay Locked Loop (DLL) on the system ASIC.

DDR-SDRAM memory parts also have DLLs on the memory devices themselves. These DLLs mean that the memory clocks output from the ASIC must be kept enabled while the memory device is in normal operating mode. Dynamically disabling the clock is not allowed.

DDR-SDRAM requires DLL blocks in the ASIC to capture the read data. The DLLs lock on to the period of a reference clock and from this can generate a temperature and voltage compensated delay. The DLL blocks can consume a reasonable amount of power. To reduce power consumption the DLLs can be disabled when the memory is not required to be accessed, for example when the SDRAM is placed into self-refresh mode. The DLL architecture also affects the amount of power that it is consumed. DLLs that continuously calibrate to the reference clock consume more power than DLLs that periodically recalibrate. For periodically recalibrating DLLs the recalibration frequency must be frequent enough to adjust for any temperature and voltage variations. In many systems the periodic DLLs are recalibrated during the auto-refresh cycles. This is because the refresh cycles are frequent enough to ensure that the DLL stays locked and enables the DLL to be calibrated while there are no read transactions in progress.

Low-power DDR-SDRAM memory has the same power reduction as low-power SDRAM.

For information on the power consumption of a particular low-power SDR-SDRAM memory device, see the respective data sheet.

For information on the power consumption on a particular low-power SDR-SDRAM memory device, see the respective data sheet.

For information on the power consumption on a particular DDR-SDRAM memory device, see the respective data sheet.