ARM PrimeCell™ MultiPort Memory Controller (PL176) Technical Reference ManualRevision: r0p1
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A.9. Example NAND flash memory timing diagrams

Figure A.8 to Figure A.13 show NAND flash timing diagrams for the K9F5608U0B Samsung device, with the timing values found in the MPMCNDTiming1/2 registers included. See the device data sheet for full timing diagrams of all transfer types supported.

Figure A.8. NAND flash timing diagram command latch cycle

Figure A.9. NAND flash timing diagram address latch cycle

Figure A.10. NAND flash timing diagram data input cycle

Figure A.11. NAND flash timing diagram data output cycle

Figure A.12. NAND flash timing diagram status read cycle

Figure A.13. NAND flash timing diagram ID read cycle

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