| Copyright © 2003 ARM Limited. All rights reserved. | ARM DDI 0269A |
| Non-Confidential | |
 PDF version | |
| Home > NAND Flash Memory Controller > Example transfers > Samsung K9F5608U0A read |
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| Home > NAND Flash Memory Controller > Example transfers > Samsung K9F5608U0A read | |||
This device uses a read sequence consisting of the following:
command phase
three address phases
a busy phase
several data read phases.
The following must be performed for a read transfer:
After reset, the MPMCStaticConfig Register is configured for the chip select to which the NAND flash device is connected:
MW is set to 8-bit
PM is left disabled
ND is set to NAND flash
PC is set to active LOW
PB and EW are left deasserted
P is set according to the device requirements.
Check the status of the NDTX bit to ensure that the NAND interface is not currently performing a transfer.
Initialize the MPMCNANDTiming1/2 Registers with the correct values for the device, or values to match the slowest NAND flash device in the system.
Initialize the command register for the read transfer:
set NDCMDV1 to 0x00 or 0x01 for
the Read 1 command, depending on the address used being in the first
or second half of the registers
leave NDCMDV2 at the previous value because it is not used
set NDCS to match the chip select of the NAND flash device
set NDADDRPH to 0x3, because
three address vectors are required
set NDDATAPH to one because there is a data phase in the transfer
set NDCMDPH2 to zero because there is no second command phase
set NDIDRD and NDSHORTRD to zero because this is a standard data read that uses the ready/busy output to control the read data timing
set NDTXRW to zero because this is a read transfer.
Initialize the NDADDRV1-3 sections of the MPMCNANDAddress1 Register with the three address values required for the transfer. The NDADDRV4-5 sections can remain with their previous values because they are not used.
Perform a single transfer to the chip select connected to the NAND flash device, with the lower address bits set to the Start value. This NAND flash interface waits to be granted control of the external bus, performs the command and address phases, and waits for the read data to be copied to the output registers as indicated by the ready/busy output of the memory device. When the device busy phase has completed, it is ready to perform a data transfer.
Perform as many reads as required, up to a maximum of 528 bytes for the full page.
Perform a single transfer to the Stop location on the NAND flash chip select to indicate that the read transfer has completed. The control signals are then deasserted, including the chip select, and the NDTX bit is cleared to indicate that no NAND flash transfers are being performed.
| Copyright © 2003 ARM Limited. All rights reserved. | ARM DDI 0269A |
| Non-Confidential | |
| PDF version | |
| Home > NAND Flash Memory Controller > Example transfers > Samsung K9F5608U0A read |