The PrimeCell MPMC generates byte lane control signals nMPMCBLSOUT[3:0] according to:

Doubleword transfers are the largest size transfers supported by the 64-bit ports of the MPMC, and word transfers the largest supported by the 32-bit ports. Any access attempted with a size greater than the port size causes an ERROR response to be generated. Each memory chip select can be 8, 16, or 32 bits wide. The type of memory used determines how the nMPMCSTWEOUT and nMPMCBLSOUT signals are connected to provide byte, halfword and word access. For read accesses, you must control the nMPMCBLSOUT signals by driving them either all HIGH, or all LOW. This is done by programming the Byte Lane State (PB) bit within the MPMCStaticConfig0-3 Registers. Memory banks constructed from 8-bit or non byte-partitioned memory devices and Memory banks constructed from 16 or 32-bit memory devices explain why different connections are required, in respect of nMPMCSTWEOUT and nMPMCBLSOUT[3:0], for different memory configurations.