| Copyright © 2003 ARM Limited. All rights reserved. | ARM DDI 0269A |
| Non-Confidential | |
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Each bank of the PrimeCell MPMC must be configured for external transfer wait states in read and write accesses. This is achieved by programming the appropriate fields of the bank control registers:
MPMCStaticConfig[n]
MPMCStaticWaitWen[n]
MPMCStaticWaitOen[n]
MPMCStaticWaitRd[n]
MPMCStaticWaitWr[n]
MPMCStaticWaitPage[n]
MPMCStaticWaitTurn[n]
MPMCStaticExtendedWait.
The number of cycles in which an AMBA transfer completes is controlled by two additional factors:
access width
external memory width.
Each bank of the PrimeCell MPMC has a programmable enable for the extended wait (EW):
The WAITRD wait state field of the MPMCStaticWaitRd0-3 Registers can be programmed to select from 1 to 32 wait states for either:
read memory accesses to SRAM and ROM
the initial read access to page mode devices.
The WAITWR wait state field of the MPMCStaticWaitWr0-3 Registers can be programmed to select from 1 to 32 wait states for write access to SRAM.
The MPMCStaticWaitPage0-3 Registers can be programmed to select from 1 to 32 wait states for page mode accesses.
| Copyright © 2003 ARM Limited. All rights reserved. | ARM DDI 0269A |
| Non-Confidential | |
| PDF version | |
| Home > Static Memory Controller > Static memory initialization > Wait state generation |