ARM PrimeCell™ MultiPort Memory Controller (PL176) Technical Reference ManualRevision: r0p1
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5.7. Byte lane control and data bus steering

Table 5.33 to Table 5.44 show the relationship of signals HSIZE[2:0], HADDR[1:0], MPMCADDROUT[1:0], and nMPMCBLSOUT[3:0] and mapping of data between the AHB system data bus and the external memory data bus. This mapping applies to both the static and dynamic memory controllers.

Table 5.33. Little-endian read, 8-bit external bus

Internal transfer widthAccess: Read, little-endian, 8-bit external busExternal data mapping on to system data bus HRDATA to MPMCDATA
HSIZE [2:0]HADDR [1:0]MPMCADDROUT[1:0]nMPMCBLS OUT[0][31:24][23:16][15:8][7:0]
Word (4 transfers)010 010 010 010-- -- -- --11 10 01 000 0 0 0[7:0] - - -- [7:0] - -- - [7:0] -- - - [7:0]
Halfword (2 transfers)0011-11 100 0[7:0] -- [7:0]- -- -
Halfword (2 transfers)0010-01 000 0- -- -[7:0] -- [7:0]
Byte00011110[7:0]---
Byte00010100-[7:0]--
Byte00001010--[7:0]-
Byte00000000---[7:0]

Table 5.34. Little-endian read, 16-bit external bus

Internal transfer width

Access: Read, little-endian, 16-bit external bus

External data mapping on to system data bus HRDATA to MPMCDATA

HSIZE [2:0]HADDR [1:0]MPMCADDROUT[0]nMPMCBLS OUT[1:0][31:4][23:16][15:8][7:0]
Word (2 transfers)010 010-- --1 000 00[15:8] -[7:0] -- [15:8]- [7:0]
Halfword0011-100[15:8][7:0]--
Halfword0010-000--[15:8][7:0]
Byte00011101[15:8]---
Byte00010110-[7:0]--
Byte00001001--[15:8]-
Byte00000010---[7:0]

Table 5.35. Little-endian read, 32-bit external bus

Internal transfer width

Access: Read, little-endian, 32-bit external bus

External data mapping on to system data bus HRDATA to MPMCDATA

HSIZE [2:0]HADDR [1:0]nMPMCBLS OUT[3:0][31:24][23:16][15:8][7:0]
Word010--0000[31:24][23:16][15:8][7:0]
Halfword0011-0011[31:24][23:16]--
Halfword0010-1100--[15:8][7:0]
Byte000110111[31:24]---
Byte000101011-[23:16]--
Byte000011101--[15:8]-
Byte000001110---[7:0]

Table 5.36. Little-endian write, 8-bit external bus

Internal transfer width

Access: Write, little-endian, 8-bit external bus

System data mapping on to external data bus MPMCDATA to HRDATA
HSIZE [2:0]HADDR [1:0]MPMCADDROUT[1:0]nMPMCBLSOUT[0][31:24][23:16][15:8][7:0]
Word (4 transfers)010 010 010 010-- -- -- --11 10 01 000 0 0 0- - - -- - - -- - - -[31:24] [23:16] [15:8] [7:0]
Halfword (2 transfers)0011-11 100 0- -- -- -[31:24] [23:16]
Halfword (2 transfers)0010-01 000 0- -- -- -[15:8] [7:0]
Byte00011110---[31:24]
Byte00010100---[23:16]
Byte00001010---[15:8]
Byte00000000---[7:0]

Table 5.37. Little-endian write, 16-bit external bus

Internal transfer width

Access: Write, little-endian, 16-bit external bus

System data mapping on to external data bus MPMCDATA to HRDATA

HSIZE [2:0]HADDR [1:0]MPMCADDROUT[0]nMPMCBLSOUT[1:0][31:24][23:16][15:8][7:0]
Word (2 transfers)010 010-- --1 000 00- -- -[31:24] [15:8][23:16] [7:0]
Halfword0011-100--[31:24][23:16]
Halfword0010-000--[15:8][7:0]
Byte00011101--[31:24]-
Byte00010110---[23:16]
Byte00001001--[15:8]-
Byte00000010---[7:0]

Table 5.38. Little-endian write, 32-bit external bus

Internal transfer width

Access: Write, little-endian, 32-bit external bus

System data mapping on to external data bus MPMCDATA to HRDATA

HSIZE [2:0]HADDR [1:0]nMPMCBLSOUT[3:0][31:24][23:16][15:8][7:0]
Word010--0000[31:24][23:16][15:8][7:0]
Halfword0011-0011[31:24][23:16]--
Halfword0010-1100--[15:8][7:0]
Byte000110111[31:24]---
Byte000101011-[23:16]--
Byte000011101--[15:8]-
Byte000001110---[7:0]

Table 5.39. Big-endian read, 8-bit external bus

Internal transfer width

Access: Read, big-endian, 8-bit external bus

External data mapping on to system data bus HRDATA to MPMCDATA
HSIZE [2:0]HADDR [1:0]MPMCADDROUT[1:0]nMPMCBLSOUT[0][31:24][23:16][15:8][7:0]
Word (4 transfers)010 010 010 010-- -- -- --11 10 01 000 0 0 0- - - [7:0]- - [7:0] -- [7:0] - -[7:0]- - -
Halfword (2 transfers)0011-11 100 0- -- -- [7:0][7:0] -
Halfword (2 transfers)0010-01 000 0- [7:0][7:0] -- -- -
Byte00011110---[7:0]
Byte00010100--[7:0]-
Byte00001010-[7:0]--
Byte00000000[7:0]---

Table 5.40. Big-endian read, 16-bit external bus

Internal transfer widthAccess: Read, Big-endian, 16-bit external bus External data mapping on to system data bus HRDATA to MPMCDATA
HSIZE [2:0]HADDR [1:0]MPMCADDROUT[0]nMPMCBLS OUT[1:0][31:24][23:16][15:8][7:0]
Word (2 transfers)010 010-- --1 000 00- [15:8]- [7:0][15:8] -[7:0] -
Halfword0011-100--[15:8][7:0]
Halfword0010-000[15:8][7:0]--
Byte00011110---[7:0]
Byte00010101--[15:8]-
Byte00001010-[7:0]--
Byte00000001[15:8]---

Table 5.41. Big-endian read, 32-bit external bus

Internal transfer width

Access: Read, big-endian, 32-bit external bus

External data mapping on to system data bus HRDATA to MPMCDATA
HSIZE [2:0]HADDR [1:0]nMPMCBLS OUT[3:0][31:24][23:16][15:8][7:0]
Word010--0000[31:24][23:16][15:8][7:0]
Halfword0011-1100--[15:8][7:0]
Halfword 0010-0011[31:24][23:16]--
Byte000111110---[7:0]
Byte000101101--[15:8]-
Byte000011011-[23:16]--
Byte000000111[31:24]---

Table 5.42. Big-endian write, 8-bit external bus

Internal transfer width

Access: Write, big-endian, 8-bit external bus

System data mapping on to external data bus MPMCDATA to HRDATA
HSIZE [2:0]HADDR [1:0]MPMCADDROUT[1:0]nMPMCBLSOUT[0][31:24][23:16][15:8][7:0]
Word (4 transfers)010 010 010 010-- -- -- --11 10 01 000 0 0 0- - - -- - - -- - - -[7:0] [15:8] [23:16] [31:24]
Halfword (2 transfers)0011-11 100 0- -- -- -[7:0] [15:8]
Halfword (2 transfers)0010-01 000 0- -- -- -[23:16] [31:24]
Byte00011110---[7:0]
Byte00010100---[15:8]
Byte00001010---[23:16]
Byte00000000---[31:24]

Table 5.43. Big-endian write, 16-bit external bus

Internal transfer width

Access: Write, big-endian, 16-bit external bus

System data mapping on to external data bus MPMCDATA to HRDATA
HSIZE [2:0]HADDR [1:0]MPMCADDROUT[0]nMPMCBLSOUT[1:0][31:24][23:16][15:8][7:0]
Word (2 transfers)010 010-- --1 000 00- -- -[15:8] [31:24][7:0] [23:16]
Halfword0011-100--[15:8][7:0]
Halfword0010-000--[31:24][23:16]
Byte00011110---[7:0]
Byte00010101--[15:8]-
Byte00001010---[23:16]
Byte00000001--[31:24]-

Table 5.44. Big-endian write, 32-bit external bus

Internal transfer width

Access: Write, big-endian, 32-bit external bus

System data mapping on to external data bus MPMCDATA to HRDATA
HSIZE [2:0]HADDR [1:0]nMPMCBLSOUT[3:0][31:24][23:16][15:8][7:0]
Word010--0000[31:24][23:16][15:8][7:0]
Halfword0011-1100--[15:8][7:0]
Halfword0010-0011[31:24][23:16]--
Byte000111110---[7:0]
Byte000101101--[15:8]-
Byte000011011-[23:16]--
Byte000000111[31:24]---

Table 5.45 to Table 5.56 show the relationship of signals HSIZE[2:0], HADDR[2:0], MPMCADDROUT[1:0], and nMPMCBLSOUT[3:0], and mapping of data between a 64-bit AHB port data bus and the external SRAM data bus.

Table 5.45. Little-endian read, 8-bit external bus

Internal transfer width

Access: Read, little-endian, 8-bit external bus

External data mapping on to system data bus HRDATA to MPMCDATA
HSIZE [2:0]HADDR [2:0]MPMC ADDR OUT[2:0]nMPMC BLS OUT[0][63: 56][55: 48][47: 40][39: 32][31: 24][23: 16][15: 8][7: 0]
Doubleword (8 transfers)011 011 011 011 011 011 011 011--- --- --- --- --- --- --- ---111 110 101 100 011 010 001 0000 0 0 0 0 0 0 0[7:0] - - - - - - -- [7:0] - - - - - -- - [7:0] - - - - -- - - [7:0] - - - -- - - - [7:0] - - -- - - - - [7:0] - -- - - - - - [7:0] -- - - - - - - [7:0]
Word (4 transfers)010 010 010 0101-- 1-- 1-- 1--111 110 101 1000 0 0 0[7:0] - - -- [7:0] - -- - [7:0] -- - - [7:0]- - - -- - - -- - - -- - - -
Word (4 transfers)010 010 010 0100-- 0-- 0-- 0--011 010 001 0000 0 0 0- - - -- - - -- - - -- - - -[7:0] - - -- [7:0] - -- - [7:0] -- - - [7:0]
Halfword (2 transfers)001 00111- 11-111 1100 0[7:0] -- [7:0]- -- -- -- -- -- -
Halfword (2 transfers)001 00110- 10-101 1000 0- -- -[7:0] -- [7:0]- -- -- -- -
Halfword (2 transfers)001 00101- 01-011 0100 0- -- -- -- -[7:0] -- [7:0]- -- -
Halfword (2 transfers)001 00100- 00-001 0000 0- -- -- -- -- -- -[7:0] -- [7:0]
Byte0001111110[7:0]-------
Byte0001101100-[7:0]------
Byte0001011010--[7:0]-----
Byte0001001000---[7:0]----
Byte0000110110----[7:0]---
Byte0000100100-----[7:0]--
Byte0000010010------[7:0]-
Byte0000000000-------[7:0]

Table 5.46. Little-endian read, 16-bit external bus

Internal transfer width

Access: Read, little-endian, 16-bit external bus

External data mapping on to system data bus HRDATA to MPMCDATA
HSIZE [2:0]HADDR [2:0]MPMC ADDR OUT[1:0]nMPMC BLS OUT[1:0][63: 56][55: 48][47: 40][39: 32][31: 24][23: 16][15: 8][7: 0]
Doubleword (4 transfers)011 011 011 011 --- --- --- ---11 10 01 0000 00 00 00[15: 8] - - -[7:0] - - -- [15: 8] - -- [7:0] - -- - [15: 8] -- - [7:0] -- - - [15: 8]- - - [7:0]
Word (2 transfers)010 0101-- 1--11 1000 00[15: 8] -[7:0] -- [15: 8]- [7:0]- -- -- -- -
Word (2 transfers)010 0100-- 0--01 0000 00- -- -- -- -[15: 8] -[7:0] -- [15: 8]- [7:0]
Halfword 00111-1100[15: 8][7:0]------
Halfword 00110-1000--[15: 8][7:0]----
Halfword 00101-0100----[15: 8][7:0]--
Halfword 00100-0000------[15: 8][7:0]
Byte0001111101[15: 8]-------
Byte0001101110-[7:0]------
Byte0001011001--[15: 8]-----
Byte0001001010---[7:0]----
Byte0000110101----[15: 8]---
Byte0000100110-----[7:0]--
Byte0000010001------[15: 8]-
Byte0000000010-------[7:0]

Table 5.47. Little-endian read, 32-bit external bus

Internal transfer width

Access: Read, little-endian, 32-bit external bus

External data mapping on to system data bus HRDATA to MPMCDATA
HSIZE [2:0]HADDR [2:0]MPMC ADDR OUT[0]nMPMC BLS OUT[3:0][63: 56][55: 48][47: 40][39: 32][31: 24][23: 16][15: 8][7: 0]
Doubleword (2 transfers)011 011 --- ---1 10000 0000[31: 24] -[23: 16] -[15: 8] -[7:0] -- [31: 24]- [23: 16]- [15: 8]- [7:0]
Word 010 1--10000 [31: 24][23: 16][15: 8][7:0]----
Word 010 0--00000----[31: 24][23: 16][15: 8][7:0]
Halfword 00111-10011[31: 24][23: 16]------
Halfword 00110-11100--[15: 8][7:0]----
Halfword 00101-00011----[31: 24][23: 16]--
Halfword 00100-01100------[15: 8][7:0]
Byte00011110111[31: 24]-------
Byte00011011011-[23: 16]------
Byte00010111101--[15: 8]-----
Byte00010011110---[7:0]----
Byte00001100111----[31: 24]---
Byte00001001011-----[23: 16]--
Byte00000101101------[15: 8]-
Byte00000001110-------[7:0]

Table 5.48. Little-endian write, 8-bit external bus

Internal transfer width

Access: Write, little-endian, 8-bit external bus

System data mapping on to external data bus MPMCDATA to HRDATA
HSIZE [2:0]HADDR [2:0]MPMCADDR OUT[2:0]nMPMCBLS OUT[0][31:24][23:16][15:8][7:0]
Doubleword (8 transfers)011 011 011 011 011 011 011 011--- --- --- --- --- --- --- ---111 110 101 100 011 010 001 0000 0 0 0 0 0 0 0- - - - - - - -- - - - - - - -- - - - - - - -[63:56] [55:48] [47:40] [39:32] [31:24] [23:16] [15:8] [7:0]
Word (4 transfers)010 010 010 0101-- 1-- 1-- 1--111 110 101 1000 0 0 0- - - -- - - -- - - -[63:56] [55:48] [47:40] [39:32]
Word (4 transfers)010 010 010 0100-- 0-- 0-- 0--011 010 001 0000 0 0 0- - - -- - - -- - - -[31:24] [23:16] [15:8] [7:0]
Halfword (2 transfers)001 00111- 11-111 1100 0- -- -- -[63:56] [55:48]
Halfword (2 transfers)001 00110- 10-101 1000 0- -- -- -[47:40] [39:32]
Halfword (2 transfers)001 00101- 01-011 0100 0- -- -- -[31:24] [23:16]
Halfword (2 transfers)001 00100- 00-001 0000 0- -- -- -[15:8] [7:0]
Byte0001111110---[63:56]
Byte0001101100---[55:48]
Byte0001011010---[47:40]
Byte0001001000---[39:32]
Byte0000110110---[31:24]
Byte0000100100---[23:16]
Byte0000010010---[15:8]
Byte0000000000---[7:0]

Table 5.49. Little-endian write, 16-bit external bus

Internal transfer width

Access: Write, little-endian, 16-bit external bus

System data mapping on to external data bus MPMCDATA to HRDATA
HSIZE [2:0]HADDR [2:0]MPMCADDR OUT[1:0]nMPMCBLS OUT[1:0][31:24][23:16][15:8][7:0]
Doubleword (4 transfers)011 011 011 011--- --- --- ---11 10 01 0000 00 00 00- - - -- - - -[63:56] [47:40] [31:24] [15:8][55:48] [39:32] [23:16] [7:0]
Word (2 transfers)010 0101-- 1--11 1000 00- -- -[63:56] [47:40][55:48] [39:32]
Word (2 transfers)010 0100-- 0--01 0000 00- -- -[31:24] [15:8][23:16] [7:0]
Halfword00111-1100--[63:56][55:48]
Halfword00110-1000--[47:40][39:32]
Halfword 00101-0100--[31:24][23:16]
Halfword 00100-0000--[15:8][7:0]
Byte0001111101--[63:56]-
Byte0001101110---[55:48]
Byte0001011001--[47:40]-
Byte0001001010---[39:32]
Byte0000110101--[31:24]-
Byte0000100110---[23:16]
Byte0000010001--[15:8]-
Byte0000000010---[7:0]

Table 5.50. Little-endian write, 32-bit external bus

Internal transfer width

Access: Write, little-endian, 32-bit external bus

System data mapping on to external data bus MPMCDATA to HRDATA
HSIZE [2:0]HADDR [2:0]nMPMCBLS OUT[3:0][31:24][23:16][15:8][7:0]
Doubleword (2 transfers)011 011--- ---0000 0000[63:56] [47:40][55:48] [39:32][31:24] [15:8][23:16] [7:0]
Word010 1--0000 [63:56][55:48][47:40][39:32]
Word010 0--0000 [31:24][23:16][15:8][7:0]
Halfword00111-0011[63:56][55:48]--
Halfword00110-1100--[47:40][39:32]
Halfword 00101-0011[31:24][23:16]--
Halfword 00100-1100--[15:8][7:0]
Byte0001110111[63:56]---
Byte0001101011-[55:48]--
Byte0001011101--[47:40]-
Byte0001001110---[39:32]
Byte0000110111[31:24]---
Byte0000101011-[23:16]--
Byte0000011101--[15:8]-
Byte0000001110---[7:0]

Table 5.51. Big-endian read, 8-bit external bus

Internal transfer width

Access: Read, Big-endian, 8-bit external bus

External data mapping on to system data bus HRDATA to MPMCDATA
HSIZE [2:0]HADDR [2:0]MPMC ADDR OUT[2:0]nMPMC BLS OUT[0][63: 56][55: 48][47: 40][39: 32][31: 24][23: 16][15: 8][7: 0]
Doubleword (8 transfers)011 011 011 011 011 011 011 011--- --- --- --- --- --- --- ---111 110 101 100 011 010 001 0000 0 0 0 0 0 0 0- - - [7:0] - - - -- - [7:0] - - - - -- [7:0] - - - - - -[7:0] - - - - - - -- - - - - - - [7:0]- - - - - - [7:0] -- - - - - [7:0] - -- - - - [7:0]- - -
Word (4 transfers)010 010 010 0101-- 1-- 1-- 1--111 110 101 1000 0 0 0- - - [7:0]- - [7:0] -- [7:0] - -[7:0] - - -- - - -- - - -- - - -- - - -
Word (4 transfers)010 010 010 0100-- 0-- 0-- 0--011 010 001 0000 0 0 0- - - -- - - -- - - -- - - -- - - [7:0]- - [7:0] -- [7:0] - -[7:0] - - -
Halfword (2 transfers)001 00111- 11-111 1100 0- -- -- [7:0][7:0] -- -- -- -- -
Halfword (2 transfers)001 00110- 10-101 1000 0- [7:0][7:0] -- -- -- -- -- -- -
Halfword (2 transfers)001 00101- 01-011 0100 0- -- -- -- -- -- -- [7:0][7:0] -
Halfword (2 transfers)001 00100- 00-001 0000 0- -- -- -- -- [7:0][7:0] -- -- -
Byte0001111110---[7:0]----
Byte0001101100--[7:0]-----
Byte0001011010-[7:0]------
Byte0001001000[7:0]-------
Byte0000110110-------[7:0]
Byte0000100100------[7:0]-
Byte0000010000-----[7:0]--
Byte0000000000----[7:0]---

Table 5.52. Big-endian read, 16-bit external bus

Internal transfer width

Access: Read, Big-endian, 16-bit external bus

External data mapping on to system data bus HRDATA to MPMCDATA
HSIZE [2:0]HADDR [2:0]MPMC ADDR OUT[1:0]nMPMC BLS OUT[1:0][63: 56][55: 48][47: 40][39: 32][31: 24][23: 16][15: 8][7: 0]
Doubleword (4 transfers)011 011 011 011 --- --- --- ---11 10 01 0000 00 00 00- [15: 8] - -- [7:0] - -[15: 8] - - -[7:0] - - -- - - [15: 8]- - - [7:0]- - [15: 8] -- - [7:0] -
Word (2 transfers)010 0101-- 1--11 1000 00- [15: 8]- [7:0][15: 8] -[7:0] -- -- -- -- -
Word (2 transfers)010 0100-- 0--01 0000 00- -- -- -- -- [15: 8]- [7:0][15: 8] -[7:0] -
Halfword 00111-1100--[15: 8][7:0]----
Halfword 00110-1000[15: 8][7:0]------
Halfword00101-0100------[15: 8][7:0]
Halfword 00100-0000----[15: 8][7:0]--
Byte0001111110---[7:0]----
Byte0001101101--[15: 8]-----
Byte0001011010-[7:0]------
Byte0001001001[15: 8]-------
Byte0000110110-------[7:0]
Byte0000100101------[15: 8]-
Byte0000010010-----[7:0]--
Byte0000000001----[15: 8]---

Table 5.53. Big-endian read, 32-bit external bus

Internal transfer width

Access: Read, Big-endian, 32-bit external bus

External data mapping on to system data bus HRDATA to MPMCDATA
HSIZE [2:0]HADDR [2:0]MPMC ADDR OUT[0]nMPMC BLS OUT[3:0][63: 56][55: 48][47: 40][39: 32][31: 24][23: 16][15: 8][7: 0]
Doubleword (2 transfers)011 011 --- ---1 10000 0000[31: 24] -[23: 16] -[15: 8] -[7:0] -- [31: 24]- [23: 16]- [15: 8]- [7:0]
Word 010 1--10000 [31: 24][23: 16][15: 8][7:0]----
Word 010 0--00000 ----[31: 24][23: 16][15: 8][7:0]
Halfword 00111-11100--[15: 8][7:0]----
Halfword 00110-10011[31: 24][23: 16]------
Halfword 00101-01100------[15: 8][7:0]
Halfword 00100-00011----[31: 24][23: 16]--
Byte00011111110---[7:0]----
Byte00011011101--[15: 8]-----
Byte00010111011-[23: 16]------
Byte00010010111[31: 24]-------
Byte00001101110-------[7:0]
Byte00001001101------[15: 8]-
Byte00000101011-----[23: 16]--
Byte00000000111----[31: 24]---

Table 5.54. Big-endian write, 8-bit external bus

Internal transfer width

Access: Write, little-endian, 8-bit external bus

System data mapping on to external data bus MPMCDATA to HRDATA
HSIZE [2:0]HADDR [2:0]MPMCADDR OUT[2:0]nMPMCBLS OUT[0][31:24][23:16][15:8][7:0]
Doubleword (8 transfers)011 011 011 011 011 011 011 011--- --- --- --- --- --- --- ---111 110 101 100 011 010 001 0000 0 0 0 0 0 0 0- - - - - - - -- - - - - - - -- - - - - - - -[39:32] [47:40] [55:48] [63:56] [7:0] [15:8] [23:16] [31:24]
Word (4 transfers)010 010 010 0101-- 1-- 1-- 1--111 110 101 1000 0 0 0- - - -- - - -- - - -[39:32] [47:40] [55:48] [63:56]
Word (4 transfers)010 010 010 0100-- 0-- 0-- 0--011 010 001 0000 0 0 0- - - -- - - -- - - -[7:0] [15:8] [23:16] [31:24]
Halfword (2 transfers)001 00111- 11-111 1100 0- -- -- -[39:32] [47:40]
Halfword (2 transfers)001 00110- 10-101 1000 0- -- -- -[55:48] [63:56]
Halfword (2 transfers)001 00101- 01-011 0100 0- -- -- -[7:0] [15:8]
Halfword (2 transfers)001 00100- 00-001 0000 0- -- -- -[23:16] [31:24]
Byte0001111110---[39:32]
Byte0001101100---[47:40]
Byte0001011010---[55:48]
Byte0001001000---[63:56]
Byte0000110110---[7:0]
Byte0000100100---[15:8]
Byte0000010000---[23:16]
Byte0000000000---[31:24]

Table 5.55. Big-endian write, 16-bit external bus

Internal transfer width

Access: Write, big-endian, 16-bit external bus

System data mapping on to external data bus MPMCDATA to HRDATA
HSIZE [2:0]HADDR [2:0]MPMCADDR OUT[1:0]nMPMCBLS OUT[1:0][31:24][23:16][15:8][7:0]
Doubleword (4 transfers)011 011 011 011--- --- --- ---11 10 01 0000 00 00 00- - - -- - - -[47:40] [63:56] [15:8] [31:24][39:32] [55:48] [7:0] [23:16]
Word (2 transfers)010 0101-- 1--11 1000 00- -- -[47:40] [63:56][39:32] [55:48]
Word (2 transfers)010 0100-- 0--01 0000 00- -- -[15:8] [31:24][7:0] [23:16]
Halfword00111-1100--[47:40][39:32]
Halfword00110-1000--[63:56][55:48]
Halfword 00101-0100--[15:8][7:0]
Halfword 00100-0000--[31:24][23:16]
Byte0001111110---[39:32]
Byte0001101101--[47:40]-
Byte0001011010---[55:48]
Byte0001001001--[63:56]-
Byte0000110110---[7:0]
Byte0000100101--[15:8]-
Byte0000010010---[23:16]
Byte0000000001--[31:24]-

Table 5.56. Big-endian write, 32-bit external bus

Internal transfer width

Access: Write, big-endian, 32-bit external bus

System data mapping on to external data bus MPMCDATA to HRDATA
HSIZE [2:0]HADDR [2:0]nMPMCBLS OUT[3:0][31:24][23:16][15:8][7:0]
Doubleword (2 transfers)011 011--- ---0000 0000[63:56] [47:40][55:48] [39:32][31:24] [15:8][23:16] [7:0]
Word010 1--0000 [63:56][55:48][47:40][39:32]
Word010 0--0000 [31:24][23:16][15:8][7:0]
Halfword00111-1100--[47:40][39:32]
Halfword00110-0011[63:56][55:48]--
Halfword 00101-1100--[15:8][7:0]
Halfword 00100-0011[31:24][23:16]--
Byte0001111110---[39:32]
Byte0001101101--[47:40]-
Byte0001011011-[55:48]--
Byte0001000111[63:56]---
Byte0000111110---[7:0]
Byte0000101101--[15:8]-
Byte0000011011-[23:16]--
Byte0000000111[31:24]---

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