ARM PrimeCell™ MultiPort Memory Controller (PL176) Technical Reference Manual 3.2.22. Static Memory Output Enable Delay Registers 0-3, MPMCStaticWaitOen0-3

3.2.22. Static Memory Output Enable Delay Registers 0-3, MPMCStaticWaitOen0-3

The four-bit, read/write, MPMCStaticWaitOen0-3 Registers enable you to program the delay from the chip select or address change, whichever is later, to the output enable. It is recommended that these registers are modified during system initialization, or when there are no current or outstanding transactions. This can be ensured by waiting until the MPMC is idle, and then entering low-power or disabled mode. These registers are accessed with one wait state.

Table 3.25 shows the bit assignments for the MPMCStaticWaitOen0-3 Registers.

Table 3.25. MPMCStaticWaitOen0-3 Register bit assignments

Bits

Name

Bits	Name	Description
[31:4]	Reserved	Reserved, read undefined, do not modify.
[3:0]	Wait output enable (WAITOEN)	Delay from chip select assertion to output enable: `0x0` = No delay (reset value on nPOR) `0x1`-`0xF` = n cycle delay^[1].
^[1]The delay is WAITOEN x t_HCLK.

Description

[31:4]

Reserved

Reserved, read undefined, do not modify.

[3:0]

Wait output enable (WAITOEN)

Delay from chip select assertion to output enable:

0x0 = No delay (reset value on nPOR)

0x1-0xF = n cycle delay^[1].

^[1]The delay is WAITOEN x t_HCLK.

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