ARM PrimeCell ™ MultiPortMemory Controller (PL176) Technical Reference Manual

Revision:r0p1


Table of Contents

Preface
About this document
Intended audience
Using this manual
Product revision status
Typographical conventions
Other conventions
Further reading
Feedback
Feedback on the ARM PrimeCell MPMC(PL176)
Feedback on this document
1. Introduction
1.1. About the ARM PrimeCell MPMC (PL176)
1.1.1. Features of the PrimeCell MPMC
1.2. Supported dynamic memory devices
1.2.1. DDR-SDRAM devices
1.2.2. SDRAM devices
1.2.3. Micron style synchronous flash devices
1.2.4. Micron style V-synchronous flash devices
1.2.5. JEDEC low-power SDRAM devices
1.3. Supported static memory devices
1.3.1. Examples of ROM devices
1.3.2. Examples of page mode ROM devices
1.3.3. Examples of SRAM devices
1.3.4. Examples of flash devices
1.3.5. Examples of page mode flash devices
1.3.6. Examples of NAND flash memory devices
2. Functional Overview
2.1. PrimeCell MPMC functional description
2.1.1. Multiport memory controller block
2.1.2. AHB slave register interface
2.1.3. AHB slave memory interfaces
2.1.4. Data buffers
2.1.5. Endian and packing logic
2.1.6. Arbiter
2.1.7. MPMC state machine
2.1.8. External DLL block
2.2. Overview of a PrimeCell MPMC, ASIC,or ASSP system
2.2.1. External bus
2.2.2. Internal bus
2.3. AHB slave memory interface priority
2.3.1. AHB memory port latency
2.4. Low power operation
2.4.1. Low-power SDRAM deep sleep mode
2.4.2. Low-power SDRAM partial array refresh
2.5. Lock and semaphores
2.6. Burst types
2.7. Busy transfer type
2.8. Arbitration
2.8.1. Re-arbitration occurrence
2.8.2. Re-arbitration priority
2.9. Worst case transaction latency
2.9.1. Worst case transaction latency forthe highest priority AHB memory port
2.9.2. Worst case transaction latency forthe lower priority AHB memory ports
2.9.3. System factors affecting worst caselatency
2.10. Sharing memory bandwidth between AHBports
2.10.1. Typical AHB port TimeOut value givenbandwidth requirement
2.10.2. Typical AHB port TimeOut value givenpercentage of memory bandwidth requirement
2.10.3. Typical AHB bandwidth requirement example
2.10.4. Typical AHB percentage bandwidth example
2.11. Memory bank select
2.12. Memory map
2.12.1. Chip select 1 static memory configuration
2.12.2. Chip select 5 SDRAM memory configuration
2.12.3. Example of a boot from flash, SRAM remapped afterboot
2.12.4. Example of a boot from flash, SDRAM remapped afterboot
2.12.5. Memory aliasing
2.12.6. Unused AHB HADDRx address bits
2.13. Sharing memory interface signals
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Register descriptions
3.2.1. Control Register, MPMCControl
3.2.2. Status Register, MPMCStatus
3.2.3. Configuration Register, MPMCConfig
3.2.4. Dynamic Memory Control Register, MPMCDynamicControl
3.2.5. Dynamic Memory Refresh Timer Register,MPMCDynamicRefresh
3.2.6. Dynamic Memory Read ConfigurationRegister, MPMCDynamicReadConfig
3.2.7. Dynamic Memory Precharge Command PeriodRegister, MPMCDynamictRP
3.2.8. Dynamic Memory Active To PrechargeCommand Period Register, MPMCDynamictRAS
3.2.9. Dynamic Memory Self-refresh Exit TimeRegister, MPMCDynamictSREX
3.2.10. Dynamic Memory Write Recovery TimeRegister, MPMCDynamictWR
3.2.11. Dynamic Memory Active To Active CommandPeriod Register, MPMCDynamictRC
3.2.12. Dynamic Memory Auto-refresh PeriodRegister, MPMCDynamictRFC
3.2.13. Dynamic Memory Exit Self-refresh Register,MPMCDynamictXSR
3.2.14. Dynamic Memory Active Bank A To ActiveBank B Time Register, MPMCDynamictRRD
3.2.15. Dynamic Memory Load Mode Register,MPMCDynamictMRD
3.2.16. Dynamic Memory Last Data In To ReadCommand Time Register, MPMCDynamictCDLR
3.2.17. Static Memory Extended Wait Register,MPMCStaticExtendedWait
3.2.18. Dynamic Memory Configuration Registers0-3, MPMCDynamicConfig0-3
3.2.19. Dynamic Memory RAS and CAS Delay Registers0-3, MPMCDynamicRasCas0-3
3.2.20. Static Memory Configuration Registers0-3, MPMCStaticConfig0-3
3.2.21. Static Memory Write Enable Delay Registers0-3, MPMCStaticWaitWen0-3
3.2.22. Static Memory Output Enable DelayRegisters 0-3, MPMCStaticWaitOen0-3
3.2.23. Static Memory Read Delay Registers0-3, MPMCStaticWaitRd0-3
3.2.24. Static Memory Page Mode Read DelayRegisters 0-3, MPMCStaticWaitPage0-3
3.2.25. Static Memory Write Delay Registers0-3, MPMCStaticWaitWr0-3
3.2.26. Static Memory Turn Round Delay Registers0-3, MPMCStaticWaitTurn0-3
3.2.27. NAND Memory Control Vector Register,MPMCNANDControl
3.2.28. NAND Memory Address Vectors 1-4 Register,MPMCNANDAddress1
3.2.29. NAND Memory Address Vector 5 Register,MPMCNANDAddress2
3.2.30. NAND Memory Timing Value 1 Register,MPMCNANDTiming1
3.2.31. NAND Memory Timing Value 2 Register,MPMCNANDTiming2
3.2.32. NAND Status Information Register,MPMCNANDStatus
3.2.33. AHB Control Registers 0-9, MPMCAHBControl0-9
3.2.34. AHB Status Registers 0-9, MPMCAHBStatus0-9
3.2.35. AHB Timeout Registers 0-9, MPMCAHBTimeOut0-9
3.2.36. Additional Peripheral IdentificationRegisters, MPMCPeriphID4-7
3.2.37. Peripheral Identification Registers,MPMCPeriphID0-3
3.2.38. PrimeCell Identification Registers 0-3,MPMCPCellID0-3
4. Programmer’s Model for Test
4.1. PrimeCell MPMC test harness overview
4.1.1. AMBA test strategy
4.1.2. Non-AMBA intra-chip integration test strategy
4.1.3. Primary I/O test strategy
4.2. Production test
4.3. Test registers
4.3.1. Test Control Register, MPMCITCR
4.3.2. Test Input 1 Register, MPMCITIP1
4.3.3. Test Input 2 Register, MPMCITIP2
4.3.4. Test Output Register, MPMCITOP
4.3.5. Test Scratch Register, MPMCITScratch
5. Static Memory Controller
5.1. Static memory device selection
5.2. Write-protection
5.3. Extended wait transfers
5.4. Static memory initialization
5.4.1. Access sequencing and memory width
5.4.2. Wait state generation
5.4.3. Static memory read control
5.4.4. Static memory write control
5.4.5. Bus turnaround
5.5. Elimination of floating bytes on theexternal interface
5.6. Byte lane control
5.6.1. Memory banks constructed from 8-bitor non byte-partitioned memory devices
5.6.2. Memory banks constructed from 16 or32-bit memory devices
5.7. Byte lane control and data bus steering
6. NAND Flash Memory Controller
6.1. About the NAND flash memory controller
6.2. Initialization
6.3. Performing NAND flash transfers
6.3.1. NAND flash transfer control
6.3.2. NAND flash transfer types
6.3.3. Accessing other memory during NANDflash transfers
6.3.4. NAND flash transfer error responses
6.4. Performance implications
6.5. Example transfers
6.5.1. Samsung K9F5608U0A read
6.5.2. Samsung K9K2G08QOM page program
7. Dynamic Memory Controller
7.1. Write-protection
7.2. Access sequencing and memory width
7.3. Arbitration
7.3.1. Re-arbitration occurrence
7.3.2. Re-arbitration priority
7.4. Dynamic memory transaction latency
7.4.1. Latency tables
7.5. Transaction examples
7.5.1. Single 64-bit read from SDR-SDRAM,row open
7.5.2. Single 64-bit write to SDR-SDRAM,row open
7.5.3. Burst 4 (INCR/INCR4/WRAP4) 64-bitread from 64-bit SDR-SDRAM, row open
7.5.4. Burst 4 (INCR/INCR4/WRAP4) 64-bitread from 64-bit SDR-SDRAM, bank precharged
7.5.5. Burst 4 (INCR/INCR4/WRAP4) 64-bitread from 64-bit SDR-SDRAM, different row open
7.5.6. Burst 4 (INCR/INCR4/WRAP4) 64-bitwrite to 64-bit SDR-SDRAM, row open
7.5.7. Burst 4 (INCR/INCR4/WRAP4) 64-bitwrite to 64-bit SDR-SDRAM, bank precharged
7.5.8. Burst 4 (INCR/INCR4/WRAP4) 64-bitwrite to 64-bit SDR-SDRAM, different row open
7.5.9. Two back-to-back burst 4 (INCR/INCR4/WRAP4)64-bit read from 64-bit SDR-SDRAM, row open
7.5.10. Two back-to-back burst 4 (INCR/INCR4/WRAP4)64-bit write to 64-bit SDR-SDRAM, row open
7.6. Address mapping
7.6.1. 32-bit wide data bus address mappings(BRC) (SDR-SDRAM)
7.6.2. 32-bit wide data bus address mappings(RBC) (SDR-SDRAM)
7.6.3. 16-bit wide data bus address mappings(BRC) (SDR-SDRAM)
7.6.4. 16-bit wide data bus address mappings(RBC) (SDR-SDRAM)
7.6.5. 64-bit wide data bus address mappings(BRC) (SDR-SDRAM)
7.6.6. 64-bit wide data bus address mappings(RBC) (SDR-SDRAM)
7.6.7. 32-bit wide data bus address mappings(BSRSC) (V-SyncFlash)
7.6.8. 16-bit wide data bus address mappings(BSRSC) (V-SyncFlash)
7.6.9. 64-bit wide data bus address mappings(BSRSC) (V-SyncFlash)
7.7. SDRAM refreshing
7.8. Merged preamble and postamble
7.9. Dynamic memory controller commanddescriptions
7.10. Generic SDRAM initialization example
7.11. Micron MT48LC4M16A2 SDRAM initializationexample
7.12. Micron MT46V8M16 DDR-SDRAM initializationexample
7.13. Low-power SDRAM initialization example
7.14. Micron MT28F4M16S2 SyncFlash initializationexample
7.15. Micron SyncFlash and V-SyncFlash commands
7.15.1. Micron SyncFlash programming example
7.16. Byte lane control and data bus steering
8. Test Interface Controller
8.1. About the TIC
8.2. Sequence of events leading to entryinto TIC test mode
9. System Connectivity
9.1. On-chip signals
9.1.1. AHB register interface connectivity
9.1.2. AHB memory interface connectivity
9.1.3. TIC test connectivity
9.1.4. Pad interface connectivity
9.1.5. Reset controller connectivity
9.1.6. Boot methodologies
9.1.7. EBI connectivity
9.1.8. Static memory configuration
9.1.9. Dynamic memory configuration
9.1.10. Methodologies in setting configurationtie-offs
9.2. Self-refresh entry
9.2.1. Power Management Unit (PMU) self-refreshentry
9.2.2. Manual self-refresh entry
9.2.3. Forcing multilayer AHB masters idle
9.3. Example system
9.3.1. AHB buses
9.3.2. PMU
9.3.3. PrimeCell MPMC off-chip signals
10. Off-chip Connectivity
10.1. Memory device selection
10.1.1. DC characteristics
10.1.2. Input and output cell family
10.2. Off-chip signals
10.2.1. Pin count reduction by reducing data bus width
10.2.2. Pin count reduction by removing functionality
10.2.3. Address pin reduction
10.2.4. Chip select pin reduction
10.2.5. Device support
10.2.6. Multiplexing static and dynamic memory pins
10.2.7. Multiplexing PrimeCell MPMC pins
10.3. Clock relationships
10.4. Pad interface timing
10.4.1. On-chip timing path
10.4.2. Off-chip timing path
10.5. Pad interface methodology
10.6. Clock delay methodology
10.6.1. Clock delay
10.6.2. Clock delay advantages
10.6.3. Clock delay disadvantages
10.6.4. Data capture requirements
10.6.5. Generation of the delayed clock
10.6.6. Read data capture polarity
10.7. Command delay methodology
10.7.1. Command delay advantages
10.7.2. Command delay disadvantages
10.7.3. Generation of the delayed clock
10.7.4. Read data capture polarity
10.7.5. Command delay plus zero
10.7.6. Command delay plus zero SDRAM timingdiagrams
10.7.7. Command delay plus one
10.7.8. Command delay plus one SDRAM timingdiagrams
10.7.9. Command delay plus two
10.7.10. Command delay plus two SDRAM timingdiagrams
10.8. Clock feedback in MPMC designs
10.8.1. Generating feedback clock off-chip
10.8.2. Generating feedback clock from bidirectionalpad
10.8.3. Generating feedback clock on-chip
10.9. Memory clock and feedback clock strategy
10.9.1. Output clocks
10.9.2. Data strobes for DDR-SDRAM
10.9.3. Feedback clocks for SDR-SDRAM
10.9.4. Signal termination
10.9.5. High performance systems
10.9.6. Medium performance systems
10.9.7. Lower performance systems
10.10. NAND flash connection methodology
11. Power Strategy
11.1. Factors affecting power consumption
11.1.1. ASIC silicon process and cell library
11.1.2. ASIC design decisions
11.1.3. Memory device selection
11.1.4. PrimeCell MPMC
12. Delay Locked Loop
12.1. About the DLL
12.2. DLL calibration
12.2.1. Software programmed calibration sequence
12.3. DLL implementations
12.3.1. Absolute delay
12.3.2. Percent-of-clock delay
12.3.3. Selectable delay
A. Pad Interface Timing
A.1. About pad interface timing
A.2. Signal delay
A.3. Method to reduce delay
A.3.1. Signal skew
A.3.2. Static effects
A.3.3. Dynamic effects
A.3.4. Environmental effects
A.4. Methods to reduce skew
A.5. Methods to minimize the effects ofdelay and skew
A.6. Example SDRAM memory timing diagram
A.7. SDRAM memory timing paths
A.7.1. MPMC to SDRAM memory
A.7.2. SDRAM memory to MPMC
A.8. Example DDR-SDRAM memory timing diagram
A.9. Example NAND flash memory timing diagrams
B. Troubleshooting
B.1. Software
B.2. System
C. Signal Descriptions
C.1. AHB register signals
C.2. AHB memory signals
C.3. Miscellaneous signals
C.3.1. Tie-off signals
C.3.2. Test signals
C.3.3. Clock and reset signals
C.3.4. DLL and self-refresh signals
C.3.5. External Bus Interface signals
C.4. Pad interface and control signals
C.5. Test Interface Controller (TIC) AHBsignals
C.6. Scan test signals

List of Figures

1. Key to timing diagram conventions
2.1. PrimeCell MPMC block diagram
2.2. 64-bit master to 32-bit slave registerinterface downsizer
2.3. 32-bit master to 64-bit slave memoryinterface
2.4. PrimeCell MPMC (PL176) in an examplesystem
3.1. Peripheral identification registerbit assignment
5.1. External memory zero wait state readtiming diagram
5.2. External memory two wait state readtiming diagram
5.3. External memory two output enabledelay state read timing diagram
5.4. External memory two zero wait stateread timing diagram
5.5. External memory zero wait fixed lengthburst read timing diagram
5.6. External memory two wait states fixedlength burst read timing diagram
5.7. External memory page mode read transfertiming diagram
5.8. External memory 32-bit burst readfrom 8-bit memory timing diagram
5.9. External memory zero wait state writetiming diagram
5.10. External memory two wait state writetiming diagram
5.11. External memory two write enabledelay write timing diagram
5.12. External memory two zero wait writestiming diagram
5.13. Read followed by write (both zerowait) with no turnaround
5.14. Write followed by read (both zerowait) with no turnaround
5.15. Read followed by a write (all zerowait state) with two turnaround cycles
5.16. Memory banks constructed from 8-bitmemory
5.17. Memory banks constructed from 16-bitmemory
5.18. Memory bank constructed from 32-bitmemory
5.19. Typical memory connection diagram
7.1. Single 64-bit read from 64-bit SDR-SDRAM,row open
7.2. Single 64-bit write to 64-bit SDR-SDRAM,row open
7.3. Burst 4 (INCR4/WRAP4) 64-bit readfrom 64-bit SDR-SDRAM, row open
7.4. Burst 4 (INCRA4/WRAP4) 64-bit readfrom 64-bit SDR-SDRAM, bank precharged
7.5. Burst4 (INCRA4/WRAP4) 64-bit readfrom 64-bit SDR-SDRAM, different row open
7.6. Burst 4 (INCR4/WRAP4) 64-bit writeto 64-bit SDR-SDRAM, row open
7.7. Burst 4 (INCR/INCR4/WRAP4) 64-bitwrite to 64-bit SDR-SDRAM, bank precharged
7.8. Burst 4 (INCR/INCR4/WRAP4) 64-bitwrite to 64-bit SDR-SDRAM, different row open
7.9. Two back-to-back burst 4 (INCR/INCR4/WRAP4)64-bit read from 64-bit SDR-SDRAM, row open
7.10. Two back-to-back burst 4 (INCR/INCR4/WRAP4)64-bit write to 64-bit SDR-SDRAM, row open
9.1. System interconnection diagram
9.2. Pad interface input signals
9.3. Pad interface output signals
9.4. Pad interface dynamic memory outputsignals
9.5. Pad interface dynamic memory outputsignals
9.6. Pad interface output signals
9.7. Reset signal timing
9.8. EBI connectivity, EBI required
9.9. EBI connectivity, EBI not required
9.10. EBI signal timing
9.11. Hard coding tie-off
9.12. Setting tie-off value by a register
9.13. Setting tie-off value externally
9.14. Setting tie-off value externallyusing a shared pin
9.15. PMU self-refresh
9.16. PMU self-refresh waveforms
9.17. Forcing AHB masters idle
9.18. Example system
10.1. Clock relationships
10.2. Clock delayed pad interface readtiming
10.3. Command delayed pad interface timing
10.4. Command delay plus zero SDR-SDRAM,data captured on positive edge of HCLK
10.5. Command delayed plus one pad interfacetiming
10.6. Command delay plus one SDR-SDRAM,data captured on negative edge of HCLK
10.7. Command delay plus one SDR-SDRAM,data captured on positive edge of HCLK
10.8. Command delay plus one DDR-SDRAM,data captured on positive edge of HCLK
10.9. Command delayed plus two pad interfacetiming
10.10. Command delay plus two SDR-SDRAM,data captured on negative edge of HCLK
10.11. Command delay plus two SDR-SDRAM,data captured on positive edge of HCLK
10.12. Generating feedback clock off-chip
10.13. Generating feedback clock from bidirectionalpad
10.14. Generating feedback clock on-chip
10.15. x8 DDR-SDRAM device
10.16. Mixed width DDR-SDRAM memory devices
10.17. x8 SDRAM device
10.18. x16 SDRAM connection
10.19. x32 SDRAM interconnection
10.20. Mixed width SDRAM memory devices
10.21. SRAM and SDRAM memory devices
10.22. Medium performance systems
10.23. Lower performance systems
10.24. NAND flash connection with SRAM andSDRAM
12.1. Read data and data strobe timingdiagram
12.2. DLL calibration signals
12.3. DLL calibration waveforms
12.4. Absolute delay DLL
12.5. Percent -of-clock DLL
12.6. Selectable delay DLL
A.1. On-chip to off-chip delay for a singlesignal
A.2. On-chip to off-chip delay with skewfor a single signal
A.3. On-chip to off-chip delay with skewfor multiple signals
A.4. SDRAM timing diagram
A.5. MPMC to SDRAM memory timing path
A.6. SDRAM memory to MPMC timing path
A.7. DDR-SDRAM timing diagram
A.8. NAND flash timing diagram commandlatch cycle
A.9. NAND flash timing diagram address latch cycle
A.10. NAND flash timing diagram data input cycle
A.11. NAND flash timing diagram data output cycle
A.12. NAND flash timing diagram status read cycle
A.13. NAND flash timing diagram ID readcycle

List of Tables

2.1. AHB memory port configuration
2.2. MPMC endianness options
2.3. Read buffer enabled
2.4. Read buffer disabled
2.5. Read buffer enabled 
2.6. Read buffer disabled
2.7. Write buffer enabled
2.8. Write buffer disabled
2.9. Write buffer enabled
2.10. Write buffer disabled
2.11. Memory bank selection
3.1. PrimeCell MPMC register summary
3.2. MPMCControl Register bit assignments
3.3. MPMCStatus Register bit assignments
3.4. MPMCConfig Register bit assignments
3.5. MPMCDynamicControl Register bit assignments
3.6. Output voltage settings
3.7. MPMCDynamicRefresh Register bit assignments
3.8. MPMCDynamicReadConfig Register bit assignments
3.9. MPMCDynamictRP Register bit assignments
3.10. MPMCDynamictRAS Register bit assignments
3.11. MPMCDynamictSREX Register bit assignments
3.12. MPMCDynamictWR Register bit assignments
3.13. MPMCDynamictRC Register bit assignments
3.14. MPMCDynamictRFC Register bit assignments
3.15. MPMCDynamictXSR Register bit assignments
3.16. MPMCDynamictRRD Register bit assignments
3.17. MPMCDynamictMRD Register bit assignments
3.18. MPMCDynamictCDLR Register bit assignments
3.19. MPMCStaticExtendedWait Register bit assignments
3.20. MPMCDynamicConfig0-3 Register bit assignments
3.21. Address mapping
3.22. MPMCDynamicRasCas0-3 Register bit assignments
3.23. MPMCStaticConfig0-3 Register bit assignments
3.24. MPMCStaticWaitWen0-3 Register bit assignments
3.25. MPMCStaticWaitOen0-3 Register bit assignments
3.26. MPMCStaticWaitRd0-3 Register bit assignments
3.27. MPMCStaticWaitPage0-3 Register bit assignments
3.28. MPMCStaticWaitWr0-3 Register bit assignments 
3.29. MPMCStaticWaitTurn0-3 Register bit assignments
3.30. MPMCNANDControl Register bit assignments
3.31. MPMCNANDAddress1 Register bit assignments
3.32. MPMCNANDAddress2 Register bit assignments
3.33. MPMCNANDTiming1Register bit assignments
3.34. MPMCNANDTiming2Register bit assignments
3.35. MPMCNANDStatus Register bit assignments
3.36. MPMCAHBControl0-9 Register bit assignments
3.37. MPMCAHBStatus0-9 Register bit assignments
3.38. MPMCAHBTimeOut0-9 Register bit assignments
3.39. Conceptual MPMC Additional Peripheral ID Register bit assignments
3.40. MPMCPeriphID4 Register bit assignments
3.41. MPMCPeriphID5-7 Register bit assignments
3.42. Conceptual MPMC Peripheral ID Register bit assignments
3.43. MPMCPeriphID0 Register bit assignments
3.44. MPMCPeriphID1 Register bit assignments
3.45. MPMCPeriphID2 Register bit assignments
3.46. MPMCPeriphID3 Register bit assignments
3.47. Conceptual PrimeCell ID Register bit assignments
4.1. Test registers memory map
4.2. MPMCITCR Register bit assignments
4.3. MPMCITIP1 Register bit assignments
4.4. MPMCITIP2 Register bit assignments
4.5. MPMCITOP Register bit assignments
4.6. MPMCITScratch Register bit assignments
5.1. Static memory controller configurations
5.2. Static memory timing parameters
5.3. External memory zero wait state read
5.4. Static memory timing parameters
5.5. External memory two wait state read
5.6. Static memory timing parameters
5.7. External memory two output enable delay state
5.8. Static memory timing parameters
5.9. External memory two zero wait state reads
5.10. Static memory timing parameters
5.11. External memory zero wait fixed length burst read
5.12. Static memory timing parameters
5.13. External memory two wait states fixed length burst read
5.14. Static memory timing parameters
5.15. External memory page mode read
5.16. Static memory timing parameters
5.17. External memory 32-bit burst read from 8-bit memory
5.18. Static memory timing parameters
5.19. External memory zero wait state write
5.20. Static memory timing parameters
5.21. External memory two wait state write
5.22. Static memory timing parameters
5.23. External memory two write enable state write
5.24. Static memory timing parameters
5.25. External memory two zero wait writes
5.26. Static memory timing parameters
5.27. Read followed by write (both zero wait) with no turnarounds
5.28. Static memory timing parameters
5.29. Write followed by read (both zero wait) with no turnaround
5.30. Static memory timing parameters
5.31. Read followed by a write (all zero wait state) with two turnaroundcycles
5.32. MPMCDATAOUT[31:0] controlled by nMPMCDATAOUTEN[3:0]
5.33. Little-endian read, 8-bit external bus
5.34. Little-endian read, 16-bit external bus
5.35. Little-endian read, 32-bit external bus
5.36. Little-endian write, 8-bit external bus
5.37. Little-endian write, 16-bit external bus
5.38. Little-endian write, 32-bit external bus
5.39. Big-endian read, 8-bit external bus
5.40. Big-endian read, 16-bit external bus
5.41. Big-endian read, 32-bit external bus
5.42. Big-endian write, 8-bit external bus
5.43. Big-endian write, 16-bit external bus
5.44. Big-endian write, 32-bit external bus
5.45. Little-endian read, 8-bit external bus
5.46. Little-endian read, 16-bit external bus
5.47. Little-endian read, 32-bit external bus
5.48. Little-endian write, 8-bit external bus
5.49. Little-endian write, 16-bit external bus
5.50. Little-endian write, 32-bit external bus
5.51. Big-endian read, 8-bit external bus
5.52. Big-endian read, 16-bit external bus
5.53. Big-endian read, 32-bit external bus
5.54. Big-endian write, 8-bit external bus
5.55. Big-endian write, 16-bit external bus
5.56. Big-endian write, 32-bit external bus
6.1. NAND flash transfer addresses
7.1. 64-bit chip select width transfer latencies
7.2. 32-bit SDRAM transfer latencies
7.3. 32-bit DDR transfer latencies
7.4. Transaction details
7.5. Single 64-bit read from 64-bit SDR-SDRAM, row open
7.6. Single 64-bit write to 64-bit SDR-SDRAM, row open
7.7. Burst 4 (INCR/INCR4/WRAP4) 64-bit read from 64-bit SDR-SDRAM,row open
7.8. Burst 4 (INCR/INCR4/WRAP4) 32-bit read from 32-bit SDR-SDRAM,bank precharged
7.9. Burst 4 (INCR/INCR4/WRAP4) 64-bit read from 64-bit SDR-SDRAM, differentrow open
7.10. Burst4 (INCR/INCR4/WRAP4) 64-bit write to 64-bit SDR-SDRAM,row open
7.11. Burst 4 (INCR/INCR4/WRAP4) 64-bit write to 64-bit SDR-SDRAM,bank precharged
7.12. Burst 4 (INCR/INCR4/WRAP4) 64-bit write to 64-bit SDR-SDRAM, differentrow open
7.13. Two back-to-back burst 4 (INCR/INCR4/WRAP4) 64-bit read from64-bit SDR-SDRAM, row open
7.14. Two back-to-back burst4 (INCR/INCR4/WRAP4) 64-bit write to64-bit SDR-SDRAM, row open
7.15. Address mapping for 16M SDRAM (1Mx16, BRC)
7.16. Address mapping for 16M SDRAM (2Mx8, BRC)
7.17. Address mapping for 64M SDRAM (2Mx8, BRC)
7.18. Address mapping for 64M SDRAM (4Mx16, BRC)
7.19. Address mapping for 64M SDRAM (8Mx8, BRC)
7.20. Address mapping for 128M SDRAM (4Mx32, BRC)
7.21. Address mapping for 128M SDRAM (8Mx16, BRC)
7.22. Address mapping for 128M SDRAM (16Mx8, BRC)
7.23. Address mapping for 256M SDRAM (8Mx32, BRC)
7.24. Address mapping for 256M SDRAM (16Mx16, BRC)
7.25. Address mapping for 256M SDRAM (32Mx8, BRC)
7.26. Address mapping for 512M SDRAM (32Mx16, BRC)
7.27. Address mapping for 512M SDRAM (64Mx8, BRC)
7.28. Address mapping for 16M SDRAM (1Mx16, RBC)
7.29. Address mapping for 16M SDRAM (2Mx8, RBC)
7.30. Address mapping for 64M SDRAM (2Mx32, RBC)
7.31. Address mapping for 64M SDRAM (4Mx16, RBC)
7.32. Address mapping for 64M SDRAM (8Mx8, RBC)
7.33. Address mapping for 128M SDRAM (4Mx32, RBC)
7.34. Address mapping for 128M SDRAM (8Mx16, RBC)
7.35. Address mapping for 128M SDRAM (16Mx8, RBC)
7.36. Address mapping for 256M SDRAM (8Mx32, RBC)
7.37. Address mapping for 256M SDRAM (16Mx16, RBC)
7.38. Address mapping for 256M SDRAM (32Mx8, RBC)
7.39. Address mapping for 512M SDRAM (32Mx16, RBC)
7.40. Address mapping for 512M SDRAM (64Mx8, RBC)
7.41. Address mapping for 16M SDRAM (1Mx16, BRC)
7.42. Address mapping for 16M SDRAM (2Mx8, BRC)
7.43. Address mapping for 64M SDRAM (4Mx16, BRC)
7.44. Address mapping for 64M SDRAM (8Mx8, BRC)
7.45. Address mapping for 128M SDRAM (8Mx16, BRC)
7.46. Address mapping for 128M SDRAM (16Mx8, BRC)
7.47. Address mapping for 256M SDRAM (16Mx16, BRC)
7.48. Address mapping for 256M SDRAM (32Mx8, BRC)
7.49. Address mapping for 512M SDRAM (32Mx16, BRC)
7.50. Address mapping for 512M SDRAM (64Mx8, BRC)
7.51. Address mapping for 16M SDRAM (1Mx16, RBC)
7.52. Address mapping for 16M SDRAM (2Mx8, RBC)
7.53. Address mapping for 64M SDRAM (4Mx16, RBC)
7.54. Address mapping for 64M SDRAM (8Mx8, RBC)
7.55. Address mapping for 128M SDRAM (8Mx16, RBC)
7.56. Address mapping for 128M SDRAM (16Mx8, RBC)
7.57. Address mapping for 256M SDRAM (16Mx16, RBC)
7.58. Address mapping for 256M SDRAM (32Mx8, RBC)
7.59. Address mapping for 512M SDRAM (32Mx16, RBC)
7.60. Address mapping for 512M SDRAM (64Mx8, RBC)
7.61. Address mapping for 16M SDRAM (1Mx16, BRC)
7.62. Address mapping for 64M SDRAM (2Mx32, BRC)
7.63. Address mapping for 64M SDRAM (4Mx16, BRC)
7.64. Address mapping for 128M SDRAM (4Mx32, BRC)
7.65. Address mapping for 128M SDRAM (8Mx16, BRC)
7.66. Address mapping for 256M SDRAM (8Mx32, BRC)
7.67. Address mapping for 256M SDRAM (16Mx16, BRC)
7.68. Address mapping for 512M SDRAM (32Mx16, BRC)
7.69. Address mapping for 16M SDRAM (1Mx16, RBC)
7.70. Address mapping for 64M SDRAM (2Mx32, RBC)
7.71. Address mapping for 64M SDRAM (4Mx16, RBC)
7.72. Address mapping for 128M SDRAM (4Mx32, RBC)
7.73. Address mapping for 128M SDRAM (8Mx16, RBC)
7.74. Address mapping for 256M SDRAM (8Mx32, RBC)
7.75. Address mapping for 256M SDRAM (16Mx16, RBC)
7.76. Address mapping for 512M SDRAM (32Mx16, RBC)
7.77. Address mapping for 128M V-SyncFlash (4Mx32, BSRSC)
7.78. Address mapping for 128M V-SyncFlash (8Mx16, BSRSC)
7.79. Address mapping for 256M V-SyncFlash (8Mx32, BSRSC)
7.80. Address mapping for 256M V-SyncFlash (16Mx16, BSRSC)
7.81. Address mapping for 512M V-SyncFlash (16Mx32, BSRSC)
7.82. Address mapping for 512M V-SyncFlash (32Mx16, BSRSC)
7.83. Address mapping for 128M V-SyncFlash (8Mx16, BSRSC)
7.84. Address mapping for 256M V-SyncFlash (16Mx16, BSRSC)
7.85. Address mapping for 512M V-SyncFlash (32Mx16, BSRSC)
7.86. Address mapping for 128M V-SyncFlash (4Mx32, BSRSC)
7.87. Address mapping for 128M V-SyncFlash (8Mx16, BSRSC)
7.88. Address mapping for 256M V-SyncFlash (8Mx32, BSRSC)
7.89. Address mapping for 256M V-SyncFlash (16Mx16, BSRSC)
7.90. Address mapping for 512M V-SyncFlash (16Mx32, BSRSC)
7.91. Address mapping for 512M V-SyncFlash (32Mx16, BSRSC)
7.92. Synchronous memory commands used by MPMC
7.93. Synchronous memory commands programmed by software
7.94. SDRAM mode register settings for generic SDRAM
7.95. Field settings for Micron MT48LC4M16A2 SDRAM
7.96. SDRAM mode register settings for Micron SDRAM
7.97. Field settings for Micron MT48LC4M16A2 SDRAM
7.98. SDRAM extended mode register settings for Micron DDR-SDRAM
7.99. SDRAM mode register settings for Micron DDR-SDRAM
7.100. Field settings for Micron MT48LC4M16A2 SDRAM
7.101. SDRAM mode register settings for low-power SDRAM
7.102. Low power SDRAM extended mode register settings
7.103. Field settings for Micron MT48LC4M16A2 SDRAM
7.104. SDRAM mode register settings for SyncFlash SDRAM
7.105. SyncFlash and V-SyncFlash commands
7.106. Little-endian read, 64-bit external bus
7.107. Big-endian read, 64-bit external bus
7.108. Little-endian write, 64-bit external bus
7.109. Big-endian write, 64-bit external bus
9.1. Reset signal cycles
9.2. EBI signal cycles
9.3. MPMCStaticConfig1 Register
9.4. MPMCStaticConfig Register
9.5. MPMCDynamicReadConfig Register
9.6. MPMCDynamicConfig1 Register
9.7. MPMCDynamicRasCas1 Register
10.1. Memory device family DC characteristics
10.2. Memory device I/O cell family
10.3. Bonded out pins
10.4. Pin counts for system with dynamic and static memory, NANDflash memory, and TIC
10.5. Pin counts for system with dynamic and static memory, andTIC
10.6. Pin counts for system with dynamic and static memory, andNAND flash memory
10.7. Pin counts for system with dynamic and static memory
10.8. Pin counts for system with dynamic and NAND flash memory,and TIC
10.9. Pin counts for system with dynamic memory and TIC
10.10. Pin counts for system with static and NAND flash memory,and TIC
10.11. Pin counts for system with static memory and TIC
10.12. Pin counts for system with NAND flash memory and TIC
10.13. Pin counts for system with dynamic memory
10.14. Pin counts for system with static memory
10.15. Pin counts for system with NAND flash memory
B.1. Software troubleshooting
B.2. System troubleshooting
C.1. AHB register signal descriptions
C.2. AHB memory signal descriptions
C.3. Tie-off signal descriptions
C.4. Test signal descriptions
C.5. Clock and reset signal descriptions
C.6. DLL and self-refresh signal descriptions
C.7. EBI signal descriptions
C.8. Pad interface and control signal descriptions
C.9. TIC signal descriptions
C.10. Scan test signal descriptions

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Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A June2003 First release
Copyright ©  2003 ARM Limited. All rights reserved. ARM DDI 0269A
Non-Confidential