| PADDR[11:2] | Input | APB bridge | Subset of the AMBA APB address bus. |
| PCLK | Input | Clock generator | AMBA APB clock. |
| PENABLE | Input | APB bridge | AMBA APB enable signal. PENABLE is
asserted HIGH for one cycle of PCLK to
enable a bus transfer. |
| PRDATA[31:0] | Output | APB bridge | Unidirectional AMBA APB read data bus. |
| PRESETn | Input | Reset controller | APB bus reset signal, active LOW. |
| PSEL | Input | APB bridge | Timer module select signal from the decoder
within the APB bridge. When HIGH this signal indicates the slave
device is selected by the APB bridge, and that a data transfer is
required. |
| PWDATA[31:0] | Input | APB bridge | Unidirectional AMBA APB write data bus. |
| PWRITE | Input | APB bridge | AMBA APB transfer direction signal, indicates
a write access when HIGH, read access when LOW. |
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