4.3.1. Integration Test Control Register,
TimerITCR
This is a single-bit register used to enable integration test
mode. When in this mode, the masked interrupt outputs are directly
controlled by the integration test output set register. The bit
assignments are listed in Table 4.1.
Table 4.1. Integration Test Control Register bit assignments
| Bits | Name | Type | Function |
|---|
[31:1] | - | - | Reserved, read undefined, must be written
as zeros |
[0] | ITEN | Read/write | Integration test enable. When this bit is 1
the Dual-Timer module is placed in Integration Test Mode, otherwise
it is in normal mode. |
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