3.2.6. Masked Interrupt Status Register,
TimerXMIS
The TimerXMIS Register indicates the masked interrupt status
from the counter. This value is the logical AND of the raw interrupt
status with the Timer Interrupt Enable bit from the control register,
and is the same value which is passed to the interrupt output pin, TIMINTX. The bit assignment is listed
in Table 3.4.
Table 3.4. Masked Interrupt Status Register bit assignments
| Bits | Name | Type | Function |
|---|
| [31:1] | - | - | Reserved bits, do not modify, and ignore
on read |
[0] | TimerXMIS | Read | Enabled interrupt status from the counter |
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