The Dual-Timer module contains an integration test harness to enable the direct control of the non-AMBA module outputs for test purposes. The test harness is controlled by Integration Test Registers, TIMERITCR and TIMERITOP. This enables the connectivity of the TIMINT1, TIMINT2, and TIMINTC output signals to other modules in a SoC device to be easily verified using only transfers from the APB bus.

Figure 3-1 shows a block diagram of the output integration test harness and how TIMINT1, TIMINT2, and TIMINTC are controlled in integration test mode.