ARM Dual-Timer Module (SP804) Technical Reference Manual 2.2.4. Clock signals and clock enables

2.2.4. Clock signals and clock enables

The Dual-Timer module uses two input clocks:

PCLK is used to time all APB accesses to the Dual-Timer module registers.
TIMCLK is qualified by the clock enables, TIMCLKEN1 and TIMCLKEN2, and used to clock the prescalers, counters and their associated interrupt logic. This qualified TIMCLK rate is referred to as the effective timer clock rate. The prescaler counter only decrements on a rising edge of TIMCLK when TIMCLKENX is HIGH. The Timer counter only decrements on a rising edge of TIMCLK when TIMCLKENX is HIGH and the prescaler counter generates an enable (see Prescaler operation).

The relationship between TIMCLK and PCLK must observe the following constraints:

the rising edges of TIMCLK must be synchronous and balanced with a rising edge of PCLK
TIMCLK frequency cannot be greater than PCLK frequency.

TIMCLK, TIMCLKEN1, and TIMCLKEN2 can be used in the ways described in the following sections:

Note

Unless otherwise stated these examples use a prescale setting of divide by 1. The examples apply to either Timer1 or Timer2 in the module. TIMCLKENX refers to either TIMCLKEN1 or TIMCLKEN2.

TIMCLK equals PCLK and TIMCLKENX equals one

Figure 2.2 shows the case where TIMCLK is identical to PCLK and TIMCLKENX is permanently enabled. In this case, the counter is decremented on every TIMCLK edge.

Figure 2.2. TIMCLK equals PCLK and TIMCLKENX equals one, clock example

TIMCLK equals PCLK and TIMCLKENX is pulsed

Figure 2.3 shows the case where TIMCLK is identical to PCLK but TIMCLKENX only enables every second TIMCLK edge. In this case, the counter is decremented on every second TIMCLK rising edge.

Figure 2.3. TIMCLK equals PCLK and TIMCLKENX is pulsed, clock example

TIMCLK is less than PCLK and TIMCLKENX equals one

Figure 2.4 shows the case where TIMCLK frequency is a submultiple of the PCLK frequency but the rising edges of TIMCLK are synchronous and balanced with PCLK edges. TIMCLKENX is permanently enabled. In this case, the counter is decremented on every TIMCLK rising edge.

Figure 2.4. TIMCLK is less than PCLK and TIMCLKENX equals one, clock example

TIMCLK is less than PCLK and TIMCLKENX is pulsed

Figure 2.5 shows the case where TIMCLK frequency is a submultiple of the PCLK frequency but the rising edges of TIMCLK are synchronous and balanced with PCLK edges. TIMCLKENX only enables every second TIMCLK edge. In this case, the counter is decremented on every second TIMCLK rising edge.

Figure 2.5. TIMCLK is less than PCLK and TIMCLKENX is pulsed, clock example

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