The two FRCs are identical and contain the 32/16-bit down counter and interrupt functionality. The counter logic is clocked independently of PCLK by TIMCLK in conjunction with a clock enable TIMCLKENX although there are constraints on the relationship between PCLK and TIMCLK. See Clock signals and clock enables for details of these constraints.

Although the two FRCs are driven from a common clock, TIMCLK, each timer count rate can be independently controlled by their respective clock enables, TIMCLKEN1 and TIMCLKEN2. The prescaler in each FRC gives a further independent control of the count rate of each FRC.

See Timer operation for an operational description of the FRCs.