ARM Dual-Timer Module (SP804) Technical Reference Manual 3.2.8. Peripheral Identification Registers, TimerPeriphID0-3

3.2.8. Peripheral Identification Registers, TimerPeriphID0-3

The TimerPeriphID0-3 Registers are four 8-bit registers, that span address locations 0xFE0 - 0xFEC. The registers can conceptually be treated as a 32-bit register. The read-only registers provide the peripheral options listed in Table 3.5.

Table 3.5. Peripheral Identification Register options

Bits	Function
PartNumber[11:0]	This is used to identify the peripheral. The three digits product code `0x804` is used.
Designer ID[19:12]	This is the identification of the designer. ARM Limited is `0x41` (ASCII A).
Revision[23:20]	This is the revision number of the peripheral. The revision number starts from 0.
Configuration[31:24]	This is the configuration option of the peripheral. The configuration value is 0.

Figure 3.1 shows the bit assignments for the registers.

Figure 3.1. Peripheral identification register bit assignment

Note

When you design a system memory map you must remember that the peripheral has a 4KB-memory footprint. The 4-bit revision number is implemented by instantiating a component called RevAnd four times with its inputs tied off as appropriate, and the output sent to the read multiplexor. All memory accesses to the peripheral identification registers must be 32-bit, using the LDR instructions.

The four, 8-bit peripheral identification registers are described in the following subsections:

Timer Peripheral ID0 Register, TimerPeriphID0

The TimerPeriphID0 Register is hard-coded and the fields in the register determine the reset value. Table 3.6 lists the bit assignments of the register.

Table 3.6. Timer Peripheral ID0 Register bit assignments

Bit	Name	Description
[31:8]	-	Reserved, read undefined must be written as zeros
[7:0]	PartNumber0	These bits read back as `0x04`

Timer Peripheral ID1 Register, TimerPeriphID1

The TimerPeriphID1 Register is hard-coded and the fields in the register determine the reset value. Table 3.7 lists the bit assignments of the register.

Table 3.7. Timer Peripheral ID1 Register bit assignments

Bit	Name	Description
[31:8]	-	Reserved, read undefined, must be written as zeros
[7:4]	Designer0	These bits read back as `0x1`
[3:0]	PartNumber1	These bits read back as `0x8`

Timer Peripheral ID2 Register, TimerPeriphID2

The TimerPeriphID2 register is hard-coded and the fields in the register determine the reset value. Table 3.8 lists the bit assignment of the register.

Table 3.8. Timer Peripheral ID2 Register bit assignments

Bit	Name	Description
[31:8]	-	Reserved, read undefined, must be written as zeros
[7:4]	Revision	These bits read back as `0x1`
[3:0]	Designer1	These bits read back as `0x4`

Timer Peripheral ID3 Register, TimerPeriphID3

The TimerPeriphID3 register is hard-coded and the fields in the register determine the reset value. Table 3.9 shows the bit assignments of the register.

Table 3.9. TimerPeriphID3 register bit assignments

Bit	Name	Description
[31:8]	-	Reserved, read undefined, must be written as zeros
[7:0]	Configuration	These bits read back as `0x00`

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